source: mainline/kernel/arch/arm32/src/mach/beaglebone/beaglebone.c@ b38c079

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b38c079 was b38c079, checked in by Maurizio Lombardi <m.lombardi85@…>, 12 years ago

am335x: implementation of a generic omap uart driver derived from the am335x code.

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File size: 6.7 KB
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1/*
2 * Copyright (c) 2012 Matteo Facchinetti
3 * Copyright (c) 2012 Maurizio Lombardi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29/** @addtogroup arm32beaglebone
30 * @{
31 */
32/** @file
33 * @brief BeagleBone platform driver.
34 */
35
36#include <arch/exception.h>
37#include <arch/mach/beaglebone/beaglebone.h>
38#include <genarch/drivers/am335x/irc.h>
39#include <genarch/drivers/am335x/uart.h>
40#include <genarch/drivers/am335x/timer.h>
41#include <genarch/drivers/am335x/cm_per.h>
42#include <genarch/drivers/am335x/cm_dpll.h>
43#include <genarch/drivers/am335x/ctrl_module.h>
44#include <genarch/srln/srln.h>
45#include <interrupt.h>
46#include <ddi/ddi.h>
47#include <ddi/device.h>
48#include <mm/km.h>
49
50#define BBONE_MEMORY_START 0x80000000 /* physical */
51#define BBONE_MEMORY_SIZE 0x10000000 /* 256 MB */
52
53static void bbone_init(void);
54static void bbone_timer_irq_start(void);
55static void bbone_cpu_halt(void);
56static void bbone_get_memory_extents(uintptr_t *start, size_t *size);
57static void bbone_irq_exception(unsigned int exc_no, istate_t *istate);
58static void bbone_frame_init(void);
59static void bbone_output_init(void);
60static void bbone_input_init(void);
61static size_t bbone_get_irq_count(void);
62static const char *bbone_get_platform_name(void);
63
64static struct beaglebone {
65 am335x_irc_regs_t *irc_addr;
66 am335x_cm_per_regs_t *cm_per_addr;
67 am335x_cm_dpll_regs_t *cm_dpll_addr;
68 am335x_ctrl_module_t *ctrl_module;
69 am335x_timer_t timer;
70 omap_uart_t uart;
71} bbone;
72
73struct arm_machine_ops bbone_machine_ops = {
74 .machine_init = bbone_init,
75 .machine_timer_irq_start = bbone_timer_irq_start,
76 .machine_cpu_halt = bbone_cpu_halt,
77 .machine_get_memory_extents = bbone_get_memory_extents,
78 .machine_irq_exception = bbone_irq_exception,
79 .machine_frame_init = bbone_frame_init,
80 .machine_output_init = bbone_output_init,
81 .machine_input_init = bbone_input_init,
82 .machine_get_irq_count = bbone_get_irq_count,
83 .machine_get_platform_name = bbone_get_platform_name,
84};
85
86static void bbone_init(void)
87{
88 bbone.irc_addr = (void *) km_map(AM335x_IRC_BASE_ADDRESS,
89 AM335x_IRC_SIZE, PAGE_NOT_CACHEABLE);
90
91 bbone.cm_per_addr = (void *) km_map(AM335x_CM_PER_BASE_ADDRESS,
92 AM335x_CM_PER_SIZE, PAGE_NOT_CACHEABLE);
93
94 bbone.cm_dpll_addr = (void *) km_map(AM335x_CM_DPLL_BASE_ADDRESS,
95 AM335x_CM_DPLL_SIZE, PAGE_NOT_CACHEABLE);
96
97 bbone.ctrl_module = (void *) km_map(AM335x_CTRL_MODULE_BASE_ADDRESS,
98 AM335x_CTRL_MODULE_SIZE, PAGE_NOT_CACHEABLE);
99
100 ASSERT(bbone.irc_addr != NULL);
101 ASSERT(bbone.cm_per_addr != NULL);
102 ASSERT(bbone.cm_dpll_addr != NULL);
103 ASSERT(bbone.ctrl_module != NULL);
104
105 /* Initialize the interrupt controller */
106 am335x_irc_init(bbone.irc_addr);
107}
108
109static irq_ownership_t bbone_timer_irq_claim(irq_t *irq)
110{
111 return IRQ_ACCEPT;
112}
113
114static void bbone_timer_irq_handler(irq_t *irq)
115{
116 am335x_timer_intr_ack(&bbone.timer);
117 spinlock_unlock(&irq->lock);
118 clock();
119 spinlock_lock(&irq->lock);
120}
121
122static void bbone_timer_irq_start(void)
123{
124 unsigned sysclk_freq;
125 int rc;
126
127 /* Initialize the IRQ */
128 static irq_t timer_irq;
129 irq_initialize(&timer_irq);
130 timer_irq.devno = device_assign_devno();
131 timer_irq.inr = AM335x_DMTIMER2_IRQ;
132 timer_irq.claim = bbone_timer_irq_claim;
133 timer_irq.handler = bbone_timer_irq_handler;
134 irq_register(&timer_irq);
135
136 /* Enable the DMTIMER2 clock module */
137 am335x_clock_module_enable(bbone.cm_per_addr, DMTIMER2);
138 /* Select the SYSCLK as the clock source for the dmtimer2 module */
139 am335x_clock_source_select(bbone.cm_dpll_addr, DMTIMER2,
140 CLK_SRC_M_OSC);
141 /* Initialize the DMTIMER2 */
142 if (am335x_ctrl_module_clock_freq_get(bbone.ctrl_module,
143 &sysclk_freq) != EOK) {
144 printf("Cannot get the system clock frequency!\n");
145 return;
146 } else
147 printf("system clock running at %u hz\n", sysclk_freq);
148
149 rc = am335x_timer_init(&bbone.timer, DMTIMER2, HZ, sysclk_freq);
150 if (rc != EOK) {
151 printf("Timer initialization failed\n");
152 return;
153 }
154 /* Enable the interrupt */
155 am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
156 /* Start the timer */
157 am335x_timer_start(&bbone.timer);
158}
159
160static void bbone_cpu_halt(void)
161{
162 while (1);
163}
164
165/** Get extents of available memory.
166 *
167 * @param start Place to store memory start address (physical).
168 * @param size Place to store memory size.
169 */
170static void bbone_get_memory_extents(uintptr_t *start, size_t *size)
171{
172 *start = BBONE_MEMORY_START;
173 *size = BBONE_MEMORY_SIZE;
174}
175
176static void bbone_irq_exception(unsigned int exc_no, istate_t *istate)
177{
178 const unsigned inum = am335x_irc_inum_get(bbone.irc_addr);
179 am335x_irc_irq_ack(bbone.irc_addr);
180
181 irq_t *irq = irq_dispatch_and_lock(inum);
182 if (irq) {
183 /* The IRQ handler was found. */
184 irq->handler(irq);
185 spinlock_unlock(&irq->lock);
186 } else {
187 printf("Spurious interrupt\n");
188 }
189}
190
191static void bbone_frame_init(void)
192{
193}
194
195static void bbone_output_init(void)
196{
197 const bool ok = omap_uart_init(&bbone.uart,
198 AM335x_UART0_IRQ, AM335x_UART0_BASE_ADDRESS,
199 AM335x_UART0_SIZE);
200
201 if (ok)
202 stdout_wire(&bbone.uart.outdev);
203}
204
205static void bbone_input_init(void)
206{
207 srln_instance_t *srln_instance = srln_init();
208 if (srln_instance) {
209 indev_t *sink = stdin_wire();
210 indev_t *srln = srln_wire(srln_instance, sink);
211 omap_uart_input_wire(&bbone.uart, srln);
212 am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
213 }
214}
215
216size_t bbone_get_irq_count(void)
217{
218 return AM335x_IRC_IRQ_COUNT;
219}
220
221const char *bbone_get_platform_name(void)
222{
223 return "beaglebone";
224}
225
226/**
227 * @}
228 */
229
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