source: mainline/kernel/arch/arm32/src/interrupt.c@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was 646b996, checked in by Martin Decky <martin@…>, 16 years ago

cleanup some of the dirty hacks introduced into the arm32 port
add default configurations for the two supported arm32 variants

  • Property mode set to 100644
File size: 2.9 KB
RevLine 
[6b781c0]1/*
2 * Copyright (c) 2007 Petr Stepan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief Interrupts controlling routines.
34 */
35
36#include <arch/asm.h>
37#include <arch/regutils.h>
38#include <ddi/irq.h>
[00287cc]39#include <ddi/device.h>
[6b781c0]40#include <interrupt.h>
41
[646b996]42#ifdef MACHINE_testarm
43 #include <arch/mach/testarm/testarm.h>
44#endif
45
46#ifdef MACHINE_integratorcp
47 #include <arch/mach/integratorcp/integratorcp.h>
48#endif
49
[6b781c0]50/** Initial size of a table holding interrupt handlers. */
51#define IRQ_COUNT 8
52
53/** Disable interrupts.
54 *
55 * @return Old interrupt priority level.
56 */
57ipl_t interrupts_disable(void)
58{
59 ipl_t ipl = current_status_reg_read();
[6ac14a70]60
[6b781c0]61 current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl);
62
63 return ipl;
64}
65
66/** Enable interrupts.
67 *
68 * @return Old interrupt priority level.
69 */
70ipl_t interrupts_enable(void)
71{
72 ipl_t ipl = current_status_reg_read();
[6ac14a70]73
[6b781c0]74 current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
[00287cc]75
[6b781c0]76 return ipl;
77}
78
79/** Restore interrupt priority level.
80 *
81 * @param ipl Saved interrupt priority level.
82 */
83void interrupts_restore(ipl_t ipl)
84{
85 current_status_reg_control_write(
86 (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) |
87 (ipl & STATUS_REG_IRQ_DISABLED_BIT));
88}
89
90/** Read interrupt priority level.
91 *
92 * @return Current interrupt priority level.
93 */
94ipl_t interrupts_read(void)
95{
96 return current_status_reg_read();
97}
98
99/** Initialize basic tables for exception dispatching
100 * and starts the timer.
101 */
102void interrupt_init(void)
103{
104 irq_init(IRQ_COUNT, IRQ_COUNT);
[6ac14a70]105 machine_timer_irq_start();
[6b781c0]106}
107
108/** @}
109 */
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