[6b781c0] | 1 | /*
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| 2 | * Copyright (c) 2007 Petr Stepan
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup arm32
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Interrupts controlling routines.
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| 34 | */
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| 35 |
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| 36 | #include <arch/asm.h>
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| 37 | #include <arch/regutils.h>
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| 38 | #include <ddi/irq.h>
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[00287cc] | 39 | #include <ddi/device.h>
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[6b781c0] | 40 | #include <interrupt.h>
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| 41 |
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[646b996] | 42 | #ifdef MACHINE_testarm
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| 43 | #include <arch/mach/testarm/testarm.h>
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| 44 | #endif
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| 45 |
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| 46 | #ifdef MACHINE_integratorcp
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| 47 | #include <arch/mach/integratorcp/integratorcp.h>
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| 48 | #endif
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| 49 |
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[6b781c0] | 50 | /** Initial size of a table holding interrupt handlers. */
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| 51 | #define IRQ_COUNT 8
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| 52 |
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| 53 | /** Disable interrupts.
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| 54 | *
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| 55 | * @return Old interrupt priority level.
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| 56 | */
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| 57 | ipl_t interrupts_disable(void)
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| 58 | {
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| 59 | ipl_t ipl = current_status_reg_read();
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[6ac14a70] | 60 |
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[6b781c0] | 61 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl);
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| 62 |
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| 63 | return ipl;
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| 64 | }
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| 65 |
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| 66 | /** Enable interrupts.
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| 67 | *
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| 68 | * @return Old interrupt priority level.
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| 69 | */
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| 70 | ipl_t interrupts_enable(void)
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| 71 | {
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| 72 | ipl_t ipl = current_status_reg_read();
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[6ac14a70] | 73 |
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[6b781c0] | 74 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
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[00287cc] | 75 |
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[6b781c0] | 76 | return ipl;
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| 77 | }
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| 78 |
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| 79 | /** Restore interrupt priority level.
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| 80 | *
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| 81 | * @param ipl Saved interrupt priority level.
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| 82 | */
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| 83 | void interrupts_restore(ipl_t ipl)
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| 84 | {
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| 85 | current_status_reg_control_write(
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| 86 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) |
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| 87 | (ipl & STATUS_REG_IRQ_DISABLED_BIT));
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| 88 | }
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| 89 |
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| 90 | /** Read interrupt priority level.
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| 91 | *
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| 92 | * @return Current interrupt priority level.
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| 93 | */
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| 94 | ipl_t interrupts_read(void)
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| 95 | {
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| 96 | return current_status_reg_read();
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| 97 | }
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| 98 |
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| 99 | /** Initialize basic tables for exception dispatching
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| 100 | * and starts the timer.
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| 101 | */
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| 102 | void interrupt_init(void)
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| 103 | {
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| 104 | irq_init(IRQ_COUNT, IRQ_COUNT);
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[6ac14a70] | 105 | machine_timer_irq_start();
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[6b781c0] | 106 | }
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| 107 |
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| 108 | /** @}
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| 109 | */
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