source: mainline/kernel/arch/arm32/src/fpu_context.c@ 63e27ef

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 63e27ef was 193d280c, checked in by Martin Decky <martin@…>, 10 years ago

cstyle improvements
replace traditional K&R-style function declarations and definitions
  • Property mode set to 100644
File size: 8.2 KB
Line 
1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief arm32 FPU context
34 */
35
36#include <fpu_context.h>
37#include <arch.h>
38#include <arch/types.h>
39#include <arch/security_ext.h>
40#include <arch/cp15.h>
41#include <cpu.h>
42
43#define FPSID_IMPLEMENTER(r) ((r) >> 24)
44#define FPSID_SW_ONLY_FLAG (1 << 23)
45#define FPSID_SUBACHITECTURE(r) (((r) >> 16) & 0x7f)
46#define FPSID_PART_NUMBER(r) (((r) >> 8) & 0xff)
47#define FPSID_VARIANT(r) (((r) >> 4) 0xf)
48#define FPSID_REVISION(r) (((r) >> 0) 0xf)
49
50
51enum {
52 FPU_VFPv1 = 0x00,
53 FPU_VFPv2_COMMONv1 = 0x01,
54 FPU_VFPv3_COMMONv2 = 0x02,
55 FPU_VFPv3_NO_COMMON = 0x3, /* Does not support fpu exc. traps */
56 FPU_VFPv3_COMMONv3 = 0x4,
57};
58
59extern uint32_t fpsid_read(void);
60extern uint32_t mvfr0_read(void);
61
62enum {
63 FPEXC_EX_FLAG = (1 << 31),
64 FPEXC_ENABLED_FLAG = (1 << 30),
65};
66extern uint32_t fpexc_read(void);
67extern void fpexc_write(uint32_t);
68
69/** ARM Architecture Reference Manual ch. B4.1.58, p. B$-1551 */
70enum {
71 FPSCR_N_FLAG = (1 << 31),
72 FPSCR_Z_FLAG = (1 << 30),
73 FPSCR_C_FLAG = (1 << 29),
74 FPSCR_V_FLAG = (1 << 28),
75 FPSCR_QC_FLAG = (1 << 27),
76 FPSCR_AHP_FLAG = (1 << 26),
77 FPSCR_DN_FLAG = (1 << 25),
78 FPSCR_FZ_FLAG = (1 << 24),
79 FPSCR_ROUND_MODE_MASK = (0x3 << 22),
80 FPSCR_ROUND_TO_NEAREST = (0x0 << 22),
81 FPSCR_ROUND_TO_POS_INF = (0x1 << 22),
82 FPSCR_ROUND_TO_NEG_INF = (0x2 << 22),
83 FPSCR_ROUND_TO_ZERO = (0x3 << 22),
84 FPSCR_STRIDE_MASK = (0x3 << 20),
85 FPSCR_STRIDE_SHIFT = 20,
86 FPSCR_LEN_MASK = (0x7 << 16),
87 FPSCR_LEN_SHIFT = 16,
88 FPSCR_DENORMAL_EN_FLAG = (1 << 15),
89 FPSCR_INEXACT_EN_FLAG = (1 << 12),
90 FPSCR_UNDERFLOW_EN_FLAG = (1 << 11),
91 FPSCR_OVERFLOW_EN_FLAG = (1 << 10),
92 FPSCR_ZERO_DIV_EN_FLAG = (1 << 9),
93 FPSCR_INVALID_OP_EN_FLAG = (1 << 8),
94 FPSCR_DENORMAL_FLAG = (1 << 7),
95 FPSCR_INEXACT_FLAG = (1 << 4),
96 FPSCR_UNDERFLOW_FLAG = (1 << 3),
97 FPSCR_OVERLOW_FLAG = (1 << 2),
98 FPSCR_DIV_ZERO_FLAG = (1 << 1),
99 FPSCR_INVALID_OP_FLAG = (1 << 0),
100
101 FPSCR_EN_ALL = FPSCR_DENORMAL_EN_FLAG | FPSCR_INEXACT_EN_FLAG | FPSCR_UNDERFLOW_EN_FLAG | FPSCR_OVERFLOW_EN_FLAG | FPSCR_ZERO_DIV_EN_FLAG | FPSCR_INVALID_OP_EN_FLAG,
102};
103
104extern uint32_t fpscr_read(void);
105extern void fpscr_write(uint32_t);
106
107extern void fpu_context_save_s32(fpu_context_t *);
108extern void fpu_context_restore_s32(fpu_context_t *);
109extern void fpu_context_save_d16(fpu_context_t *);
110extern void fpu_context_restore_d16(fpu_context_t *);
111extern void fpu_context_save_d32(fpu_context_t *);
112extern void fpu_context_restore_d32(fpu_context_t *);
113
114static void (*save_context)(fpu_context_t *ctx);
115static void (*restore_context)(fpu_context_t *ctx);
116
117static int fpu_have_coprocessor_access(void)
118{
119/*
120 * The register containing the information (CPACR) is not available on armv6-
121 * rely on user decision to use CONFIG_FPU.
122 */
123#ifdef PROCESSOR_ARCH_armv7_a
124 const uint32_t cpacr = CPACR_read();
125 /* FPU needs access to coprocessor 10 and 11.
126 * Moreover they need to have same access enabled */
127 if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
128 ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
129 printf("No access to CP10 and CP11: %" PRIx32 "\n", cpacr);
130 return 0;
131 }
132#endif
133 return 1;
134}
135
136/** Enable coprocessor access. Turn both non-secure mode bit and generic access.
137 * Cortex A8 Manual says:
138 * "You must execute an Instruction Memory Barrier (IMB) sequence immediately
139 * after an update of the Coprocessor Access Control Register, see Memory
140 * Barriers in the ARM Architecture Reference Manual. You must not attempt to
141 * execute any instructions that are affected by the change of access rights
142 * between the IMB sequence and the register update."
143 * Cortex a8 TRM ch. 3.2.27. c1, Coprocessor Access Control Register
144 *
145 * @note do we need to call secure monitor here?
146 */
147static void fpu_enable_coprocessor_access(void)
148{
149/*
150 * The register containing the information (CPACR) is not available on armv6-
151 * rely on user decision to use CONFIG_FPU.
152 */
153#ifdef PROCESSOR_ARCH_armv7_a
154 /* Allow coprocessor access */
155 uint32_t cpacr = CPACR_read();
156 /* FPU needs access to coprocessor 10 and 11.
157 * Moreover, they need to have same access enabled */
158 cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
159 cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11));
160 CPACR_write(cpacr);
161#endif
162}
163
164
165void fpu_init(void)
166{
167 /* Check if we have access */
168 if (!fpu_have_coprocessor_access())
169 return;
170
171 /* Clear all fpu flags */
172 fpexc_write(0);
173 fpu_enable();
174 /* Mask all exception traps,
175 * The bits are RAZ/WI on archs that don't support fpu exc traps.
176 */
177 fpscr_write(fpscr_read() & ~FPSCR_EN_ALL);
178}
179
180void fpu_setup(void)
181{
182 /* Enable coprocessor access*/
183 fpu_enable_coprocessor_access();
184
185 /* Check if we succeeded */
186 if (!fpu_have_coprocessor_access())
187 return;
188
189 const uint32_t fpsid = fpsid_read();
190 if (fpsid & FPSID_SW_ONLY_FLAG) {
191 printf("No FPU avaiable\n");
192 return;
193 }
194 switch (FPSID_SUBACHITECTURE(fpsid)) {
195 case FPU_VFPv1:
196 printf("Detected VFPv1\n");
197 save_context = fpu_context_save_s32;
198 restore_context = fpu_context_restore_s32;
199 break;
200 case FPU_VFPv2_COMMONv1:
201 printf("Detected VFPv2\n");
202 save_context = fpu_context_save_d16;
203 restore_context = fpu_context_restore_d16;
204 break;
205 case FPU_VFPv3_COMMONv2:
206 case FPU_VFPv3_NO_COMMON:
207 case FPU_VFPv3_COMMONv3: {
208 const uint32_t mvfr0 = mvfr0_read();
209 /* See page B4-1637 */
210 if ((mvfr0 & 0xf) == 0x1) {
211 printf("Detected VFPv3+ with 16 regs\n");
212 save_context = fpu_context_save_d16;
213 restore_context = fpu_context_restore_d16;
214 } else {
215 printf("Detected VFPv3+ with 32 regs\n");
216 save_context = fpu_context_save_d32;
217 restore_context = fpu_context_restore_d32;
218 }
219 break;
220 }
221
222 }
223}
224
225bool handle_if_fpu_exception(void)
226{
227 /* Check if we have access */
228 if (!fpu_have_coprocessor_access())
229 return false;
230
231 const uint32_t fpexc = fpexc_read();
232 if (fpexc & FPEXC_ENABLED_FLAG) {
233 const uint32_t fpscr = fpscr_read();
234 printf("FPU exception\n"
235 "\tFPEXC: %" PRIx32 " FPSCR: %" PRIx32 "\n", fpexc, fpscr);
236 return false;
237 }
238#ifdef CONFIG_FPU_LAZY
239 scheduler_fpu_lazy_request();
240 return true;
241#else
242 return false;
243#endif
244}
245
246void fpu_enable(void)
247{
248 /* Check if we have access */
249 if (!fpu_have_coprocessor_access())
250 return;
251 /* Enable FPU instructions */
252 fpexc_write(fpexc_read() | FPEXC_ENABLED_FLAG);
253}
254
255void fpu_disable(void)
256{
257 /* Check if we have access */
258 if (!fpu_have_coprocessor_access())
259 return;
260 /* Disable FPU instructions */
261 fpexc_write(fpexc_read() & ~FPEXC_ENABLED_FLAG);
262}
263
264void fpu_context_save(fpu_context_t *ctx)
265{
266 /* This is only necessary if we enable fpu exceptions. */
267#if 0
268 const uint32_t fpexc = fpexc_read();
269
270 if (fpexc & FPEXC_EX_FLAG) {
271 printf("EX FPU flag is on, things will fail\n");
272 //TODO implement common subarch context saving
273 }
274#endif
275 if (save_context)
276 save_context(ctx);
277}
278
279void fpu_context_restore(fpu_context_t *ctx)
280{
281 if (restore_context)
282 restore_context(ctx);
283}
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