source: mainline/kernel/arch/arm32/src/fpu_context.c@ 97718a5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 97718a5 was 97718a5, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

arm32, fpu: Switch to new coprocessor macros.

Disable code accessing secure register.
  • Property mode set to 100644
File size: 8.8 KB
Line 
1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief arm32 FPU context
34 */
35
36#include <fpu_context.h>
37#include <arch.h>
38#include <arch/types.h>
39#include <arch/security_ext.h>
40#include <cpu.h>
41
42#define FPSID_IMPLEMENTER(r) ((r) >> 24)
43#define FPSID_SW_ONLY_FLAG (1 << 23)
44#define FPSID_SUBACHITECTURE(r) (((r) >> 16) & 0x7f)
45#define FPSID_PART_NUMBER(r) (((r) >> 8) & 0xff)
46#define FPSID_VARIANT(r) (((r) >> 4) 0xf)
47#define FPSID_REVISION(r) (((r) >> 0) 0xf)
48
49
50enum {
51 FPU_VFPv1 = 0x00,
52 FPU_VFPv2_COMMONv1 = 0x01,
53 FPU_VFPv3_COMMONv2 = 0x02,
54 FPU_VFPv3_NO_COMMON = 0x3, /* Does not support fpu exc. traps */
55 FPU_VFPv3_COMMONv3 = 0x4,
56};
57
58enum {
59 FPEXC_EX_FLAG = (1 << 31),
60 FPEXC_ENABLED_FLAG = (1 << 30),
61};
62
63/** ARM Architecture Reference Manual ch. B4.1.58, p. B$-1551 */
64enum {
65 FPSCR_N_FLAG = (1 << 31),
66 FPSCR_Z_FLAG = (1 << 30),
67 FPSCR_C_FLAG = (1 << 29),
68 FPSCR_V_FLAG = (1 << 28),
69 FPSCR_QC_FLAG = (1 << 27),
70 FPSCR_AHP_FLAG = (1 << 26),
71 FPSCR_DN_FLAG = (1 << 25),
72 FPSCR_FZ_FLAG = (1 << 24),
73 FPSCR_ROUND_MODE_MASK = (0x3 << 22),
74 FPSCR_ROUND_TO_NEAREST = (0x0 << 22),
75 FPSCR_ROUND_TO_POS_INF = (0x1 << 22),
76 FPSCR_ROUND_TO_NEG_INF = (0x2 << 22),
77 FPSCR_ROUND_TO_ZERO = (0x3 << 22),
78 FPSCR_STRIDE_MASK = (0x3 << 20),
79 FPSCR_STRIDE_SHIFT = 20,
80 FPSCR_LEN_MASK = (0x7 << 16),
81 FPSCR_LEN_SHIFT = 16,
82 FPSCR_DENORMAL_EN_FLAG = (1 << 15),
83 FPSCR_INEXACT_EN_FLAG = (1 << 12),
84 FPSCR_UNDERFLOW_EN_FLAG = (1 << 11),
85 FPSCR_OVERFLOW_EN_FLAG = (1 << 10),
86 FPSCR_ZERO_DIV_EN_FLAG = (1 << 9),
87 FPSCR_INVALID_OP_EN_FLAG = (1 << 8),
88 FPSCR_DENORMAL_FLAG = (1 << 7),
89 FPSCR_INEXACT_FLAG = (1 << 4),
90 FPSCR_UNDERFLOW_FLAG = (1 << 3),
91 FPSCR_OVERLOW_FLAG = (1 << 2),
92 FPSCR_DIV_ZERO_FLAG = (1 << 1),
93 FPSCR_INVALID_OP_FLAG = (1 << 0),
94
95 FPSCR_EN_ALL = FPSCR_DENORMAL_EN_FLAG | FPSCR_INEXACT_EN_FLAG | FPSCR_UNDERFLOW_EN_FLAG | FPSCR_OVERFLOW_EN_FLAG | FPSCR_ZERO_DIV_EN_FLAG | FPSCR_INVALID_OP_EN_FLAG,
96};
97
98extern uint32_t fpsid_read(void);
99extern uint32_t mvfr0_read(void);
100extern uint32_t fpscr_read(void);
101extern void fpscr_write(uint32_t);
102extern uint32_t fpexc_read(void);
103extern void fpexc_write(uint32_t);
104
105extern void fpu_context_save_s32(fpu_context_t *);
106extern void fpu_context_restore_s32(fpu_context_t *);
107extern void fpu_context_save_d16(fpu_context_t *);
108extern void fpu_context_restore_d16(fpu_context_t *);
109extern void fpu_context_save_d32(fpu_context_t *);
110extern void fpu_context_restore_d32(fpu_context_t *);
111
112static void (*save_context)(fpu_context_t *ctx);
113static void (*restore_context)(fpu_context_t *ctx);
114
115static int fpu_have_coprocessor_access()
116{
117/* The register containing the information (CPACR) is not available on armv6-
118 * rely on user decision to use CONFIG_FPU.
119 */
120#ifndef PROCESSOR_armv7_a
121 return 1;
122#endif
123 const uint32_t cpacr = CPACR_read();
124 /* FPU needs access to coprocessor 10 and 11.
125 * Moreover they need to have same access enabledd */
126 if (((cpacr & CPACR_CP_MASK(10)) == CPACR_CP_FULL_ACCESS(10)) &&
127 ((cpacr & CPACR_CP_MASK(11)) == CPACR_CP_FULL_ACCESS(11)))
128 return 1;
129 printf("No sccess to CP10 and CP11: %" PRIx32 "\n", cpacr);
130 return 0;
131}
132
133/** Enable coprocessor access. Turn both non-secure mode bit and generic access.
134 * Cortex A8 Manual says:
135 * "You must execute an Instruction Memory Barrier (IMB) sequence immediately
136 * after an update of the Coprocessor Access Control Register, see Memory
137 * Barriers in the ARM Architecture Reference Manual. You must not attempt to
138 * execute any instructions that are affected by the change of access rights
139 * between the IMB sequence and the register update."
140 * Cortex a8 TRM ch. 3.2.27. c1, Coprocessor Access Control Register
141 *
142 * @note do we need to call secure monitor here?
143 */
144static void fpu_enable_coprocessor_access()
145{
146/* The register containing the information (CPACR) is not available on armv6-
147 * rely on user decision to use CONFIG_FPU.
148 */
149#ifndef PROCESSOR_armv7_a
150 return;
151#endif
152#if 0
153 uint32_t cpr;
154 asm volatile("MRC p15, 0, %0, c1, c1, 0" : "=r" (cpr)::);
155 if (cpr & 1)
156 printf("We are in unsecure state, we can't change access\n");
157
158 /* Allow non-secure access */
159 uint32_t nsacr;
160 asm volatile ("mrc p15, 0, %0, c1, c1, 2" :"=r" (nsacr)::);
161 /* FPU needs access to coprocessor 10 and 11.
162 * Moreover, they need to have same access enabled */
163 nsacr |= NSACR_CP10_FLAG | NSACR_CP11_FLAG;
164 asm volatile ("mcr p15, 0, %0, c1, c1, 2" :"=r" (nsacr)::);
165
166#ifdef MACHINE_beagleboardxm
167 asm volatile ("isb" ::: "memory" );
168#endif
169#endif
170 /* Allow coprocessor access */
171 uint32_t cpacr = CPACR_read();
172 printf("CPACR before: %x\n", cpacr);
173 /* FPU needs access to coprocessor 10 and 11.
174 * Moreover, they need to have same access enabled */
175 cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
176 cpacr |= CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11);
177 CPACR_write(cpacr);
178 printf("CPACR after: %x\n", cpacr);
179
180 smc_coherence(0);
181}
182
183
184void fpu_init(void)
185{
186 /* Enable coprocessor access*/
187 fpu_enable_coprocessor_access();
188
189 /* Check if we succeeded */
190 if (!fpu_have_coprocessor_access())
191 return;
192
193 /* Clear all fpu flags */
194 fpexc_write(0);
195 fpu_enable();
196 /* Mask all exception traps,
197 * The bits are RAZ/WI on archs that don't support fpu exc traps.
198 */
199 fpscr_write(fpscr_read() & ~FPSCR_EN_ALL);
200}
201
202void fpu_setup(void)
203{
204 /* Check if we have access */
205 if (!fpu_have_coprocessor_access())
206 return;
207
208 const uint32_t fpsid = fpsid_read();
209 if (fpsid & FPSID_SW_ONLY_FLAG) {
210 printf("No FPU avaiable\n");
211 return;
212 }
213 switch (FPSID_SUBACHITECTURE(fpsid))
214 {
215 case FPU_VFPv1:
216 printf("Detected VFPv1\n");
217 save_context = fpu_context_save_s32;
218 restore_context = fpu_context_restore_s32;
219 break;
220 case FPU_VFPv2_COMMONv1:
221 printf("Detected VFPv2\n");
222 save_context = fpu_context_save_d16;
223 restore_context = fpu_context_restore_d16;
224 break;
225 case FPU_VFPv3_COMMONv2:
226 case FPU_VFPv3_NO_COMMON:
227 case FPU_VFPv3_COMMONv3: {
228 const uint32_t mvfr0 = mvfr0_read();
229 /* See page B4-1637 */
230 if ((mvfr0 & 0xf) == 0x1) {
231 printf("Detected VFPv3+ with 16 regs\n");
232 save_context = fpu_context_save_d16;
233 restore_context = fpu_context_restore_d16;
234 } else {
235 printf("Detected VFPv3+ with 32 regs\n");
236 save_context = fpu_context_save_d32;
237 restore_context = fpu_context_restore_d32;
238 }
239 break;
240 }
241
242 }
243}
244
245bool handle_if_fpu_exception(void)
246{
247 /* Check if we have access */
248 if (!fpu_have_coprocessor_access())
249 return false;
250
251 const uint32_t fpexc = fpexc_read();
252 if (fpexc & FPEXC_ENABLED_FLAG) {
253 const uint32_t fpscr = fpscr_read();
254 printf("FPU exception\n"
255 "\tFPEXC: %" PRIx32 " FPSCR: %" PRIx32 "\n", fpexc, fpscr);
256 return false;
257 }
258#ifdef CONFIG_FPU_LAZY
259 scheduler_fpu_lazy_request();
260 return true;
261#else
262 return false;
263#endif
264}
265
266void fpu_enable(void)
267{
268 /* Check if we have access */
269 if (!fpu_have_coprocessor_access())
270 return;
271 /* Enable FPU instructions */
272 fpexc_write(fpexc_read() | FPEXC_ENABLED_FLAG);
273}
274
275void fpu_disable(void)
276{
277 /* Check if we have access */
278 if (!fpu_have_coprocessor_access())
279 return;
280 /* Disable FPU instructions */
281 fpexc_write(fpexc_read() & ~FPEXC_ENABLED_FLAG);
282}
283
284void fpu_context_save(fpu_context_t *ctx)
285{
286 /* Check if we have access */
287 if (!fpu_have_coprocessor_access())
288 return;
289 const uint32_t fpexc = fpexc_read();
290
291 if (fpexc & FPEXC_EX_FLAG) {
292 printf("EX FPU flag is on, things will fail\n");
293 //TODO implement common subarch context saving
294 }
295 if (save_context)
296 save_context(ctx);
297}
298
299void fpu_context_restore(fpu_context_t *ctx)
300{
301 /* Check if we have access */
302 if (!fpu_have_coprocessor_access())
303 return;
304 if (restore_context)
305 restore_context(ctx);
306}
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