source: mainline/kernel/arch/arm32/src/fpu_context.c@ 91fcbabc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 91fcbabc was c5429fe, checked in by Jakub Jermar <jakub@…>, 7 years ago

Disambiguate architecture specific doxygroups
  • Property mode set to 100644
File size: 8.2 KB
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1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_arm32
30 * @{
31 */
32/** @file
33 * @brief arm32 FPU context
34 */
35
36#include <fpu_context.h>
37#include <arch.h>
38#include <arch/types.h>
39#include <arch/security_ext.h>
40#include <arch/cp15.h>
41#include <cpu.h>
42
43#define FPSID_IMPLEMENTER(r) ((r) >> 24)
44#define FPSID_SW_ONLY_FLAG (1 << 23)
45#define FPSID_SUBACHITECTURE(r) (((r) >> 16) & 0x7f)
46#define FPSID_PART_NUMBER(r) (((r) >> 8) & 0xff)
47#define FPSID_VARIANT(r) (((r) >> 4) 0xf)
48#define FPSID_REVISION(r) (((r) >> 0) 0xf)
49
50enum {
51 FPU_VFPv1 = 0x00,
52 FPU_VFPv2_COMMONv1 = 0x01,
53 FPU_VFPv3_COMMONv2 = 0x02,
54 FPU_VFPv3_NO_COMMON = 0x3, /* Does not support fpu exc. traps */
55 FPU_VFPv3_COMMONv3 = 0x4,
56};
57
58extern uint32_t fpsid_read(void);
59extern uint32_t mvfr0_read(void);
60
61enum {
62 FPEXC_EX_FLAG = (1 << 31),
63 FPEXC_ENABLED_FLAG = (1 << 30),
64};
65extern uint32_t fpexc_read(void);
66extern void fpexc_write(uint32_t);
67
68/** ARM Architecture Reference Manual ch. B4.1.58, p. B$-1551 */
69enum {
70 FPSCR_N_FLAG = (1 << 31),
71 FPSCR_Z_FLAG = (1 << 30),
72 FPSCR_C_FLAG = (1 << 29),
73 FPSCR_V_FLAG = (1 << 28),
74 FPSCR_QC_FLAG = (1 << 27),
75 FPSCR_AHP_FLAG = (1 << 26),
76 FPSCR_DN_FLAG = (1 << 25),
77 FPSCR_FZ_FLAG = (1 << 24),
78 FPSCR_ROUND_MODE_MASK = (0x3 << 22),
79 FPSCR_ROUND_TO_NEAREST = (0x0 << 22),
80 FPSCR_ROUND_TO_POS_INF = (0x1 << 22),
81 FPSCR_ROUND_TO_NEG_INF = (0x2 << 22),
82 FPSCR_ROUND_TO_ZERO = (0x3 << 22),
83 FPSCR_STRIDE_MASK = (0x3 << 20),
84 FPSCR_STRIDE_SHIFT = 20,
85 FPSCR_LEN_MASK = (0x7 << 16),
86 FPSCR_LEN_SHIFT = 16,
87 FPSCR_DENORMAL_EN_FLAG = (1 << 15),
88 FPSCR_INEXACT_EN_FLAG = (1 << 12),
89 FPSCR_UNDERFLOW_EN_FLAG = (1 << 11),
90 FPSCR_OVERFLOW_EN_FLAG = (1 << 10),
91 FPSCR_ZERO_DIV_EN_FLAG = (1 << 9),
92 FPSCR_INVALID_OP_EN_FLAG = (1 << 8),
93 FPSCR_DENORMAL_FLAG = (1 << 7),
94 FPSCR_INEXACT_FLAG = (1 << 4),
95 FPSCR_UNDERFLOW_FLAG = (1 << 3),
96 FPSCR_OVERLOW_FLAG = (1 << 2),
97 FPSCR_DIV_ZERO_FLAG = (1 << 1),
98 FPSCR_INVALID_OP_FLAG = (1 << 0),
99
100 FPSCR_EN_ALL = FPSCR_DENORMAL_EN_FLAG | FPSCR_INEXACT_EN_FLAG | FPSCR_UNDERFLOW_EN_FLAG | FPSCR_OVERFLOW_EN_FLAG | FPSCR_ZERO_DIV_EN_FLAG | FPSCR_INVALID_OP_EN_FLAG,
101};
102
103extern uint32_t fpscr_read(void);
104extern void fpscr_write(uint32_t);
105
106extern void fpu_context_save_s32(fpu_context_t *);
107extern void fpu_context_restore_s32(fpu_context_t *);
108extern void fpu_context_save_d16(fpu_context_t *);
109extern void fpu_context_restore_d16(fpu_context_t *);
110extern void fpu_context_save_d32(fpu_context_t *);
111extern void fpu_context_restore_d32(fpu_context_t *);
112
113static void (*save_context)(fpu_context_t *ctx);
114static void (*restore_context)(fpu_context_t *ctx);
115
116static int fpu_have_coprocessor_access(void)
117{
118 /*
119 * The register containing the information (CPACR) is not available
120 * on armv6-. Rely on user decision to use CONFIG_FPU.
121 */
122#ifdef PROCESSOR_ARCH_armv7_a
123 const uint32_t cpacr = CPACR_read();
124 /*
125 * FPU needs access to coprocessor 10 and 11.
126 * Moreover, they need to have same access enabled
127 */
128 if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
129 ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
130 printf("No access to CP10 and CP11: %" PRIx32 "\n", cpacr);
131 return 0;
132 }
133#endif
134
135 return 1;
136}
137
138/** Enable coprocessor access. Turn both non-secure mode bit and generic access.
139 * Cortex A8 Manual says:
140 * "You must execute an Instruction Memory Barrier (IMB) sequence immediately
141 * after an update of the Coprocessor Access Control Register, see Memory
142 * Barriers in the ARM Architecture Reference Manual. You must not attempt to
143 * execute any instructions that are affected by the change of access rights
144 * between the IMB sequence and the register update."
145 * Cortex a8 TRM ch. 3.2.27. c1, Coprocessor Access Control Register
146 *
147 * @note do we need to call secure monitor here?
148 */
149static void fpu_enable_coprocessor_access(void)
150{
151 /*
152 * The register containing the information (CPACR) is not available
153 * on armv6-. Rely on user decision to use CONFIG_FPU.
154 */
155#ifdef PROCESSOR_ARCH_armv7_a
156 /* Allow coprocessor access */
157 uint32_t cpacr = CPACR_read();
158 /*
159 * FPU needs access to coprocessor 10 and 11.
160 * Moreover, they need to have same access enabled
161 */
162 cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
163 cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11));
164 CPACR_write(cpacr);
165#endif
166}
167
168void fpu_init(void)
169{
170 /* Check if we have access */
171 if (!fpu_have_coprocessor_access())
172 return;
173
174 /* Clear all fpu flags */
175 fpexc_write(0);
176 fpu_enable();
177 /*
178 * Mask all exception traps,
179 * The bits are RAZ/WI on archs that don't support fpu exc traps.
180 */
181 fpscr_write(fpscr_read() & ~FPSCR_EN_ALL);
182}
183
184void fpu_setup(void)
185{
186 uint32_t mvfr0;
187
188 /* Enable coprocessor access*/
189 fpu_enable_coprocessor_access();
190
191 /* Check if we succeeded */
192 if (!fpu_have_coprocessor_access())
193 return;
194
195 const uint32_t fpsid = fpsid_read();
196 if (fpsid & FPSID_SW_ONLY_FLAG) {
197 printf("No FPU avaiable\n");
198 return;
199 }
200 switch (FPSID_SUBACHITECTURE(fpsid)) {
201 case FPU_VFPv1:
202 printf("Detected VFPv1\n");
203 save_context = fpu_context_save_s32;
204 restore_context = fpu_context_restore_s32;
205 break;
206 case FPU_VFPv2_COMMONv1:
207 printf("Detected VFPv2\n");
208 save_context = fpu_context_save_d16;
209 restore_context = fpu_context_restore_d16;
210 break;
211 case FPU_VFPv3_COMMONv2:
212 case FPU_VFPv3_NO_COMMON:
213 case FPU_VFPv3_COMMONv3:
214 mvfr0 = mvfr0_read();
215 /* See page B4-1637 */
216 if ((mvfr0 & 0xf) == 0x1) {
217 printf("Detected VFPv3+ with 16 regs\n");
218 save_context = fpu_context_save_d16;
219 restore_context = fpu_context_restore_d16;
220 } else {
221 printf("Detected VFPv3+ with 32 regs\n");
222 save_context = fpu_context_save_d32;
223 restore_context = fpu_context_restore_d32;
224 }
225 break;
226 }
227}
228
229bool handle_if_fpu_exception(void)
230{
231 /* Check if we have access */
232 if (!fpu_have_coprocessor_access())
233 return false;
234
235 const uint32_t fpexc = fpexc_read();
236 if (fpexc & FPEXC_ENABLED_FLAG) {
237 const uint32_t fpscr = fpscr_read();
238 printf("FPU exception\n"
239 "\tFPEXC: %" PRIx32 " FPSCR: %" PRIx32 "\n", fpexc, fpscr);
240 return false;
241 }
242#ifdef CONFIG_FPU_LAZY
243 scheduler_fpu_lazy_request();
244 return true;
245#else
246 return false;
247#endif
248}
249
250void fpu_enable(void)
251{
252 /* Check if we have access */
253 if (!fpu_have_coprocessor_access())
254 return;
255 /* Enable FPU instructions */
256 fpexc_write(fpexc_read() | FPEXC_ENABLED_FLAG);
257}
258
259void fpu_disable(void)
260{
261 /* Check if we have access */
262 if (!fpu_have_coprocessor_access())
263 return;
264 /* Disable FPU instructions */
265 fpexc_write(fpexc_read() & ~FPEXC_ENABLED_FLAG);
266}
267
268void fpu_context_save(fpu_context_t *ctx)
269{
270 /* This is only necessary if we enable fpu exceptions. */
271#if 0
272 const uint32_t fpexc = fpexc_read();
273
274 if (fpexc & FPEXC_EX_FLAG) {
275 printf("EX FPU flag is on, things will fail\n");
276 //TODO implement common subarch context saving
277 }
278#endif
279 if (save_context)
280 save_context(ctx);
281}
282
283void fpu_context_restore(fpu_context_t *ctx)
284{
285 if (restore_context)
286 restore_context(ctx);
287}
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