source: mainline/kernel/arch/arm32/src/fpu.s@ 7ca8422b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7ca8422b was de36fdd, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

arm32: Move fpu handling code to .s file.

restrict kernel fpu instructions to asm files.

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/*
2 * Copyright (c) 2013 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29.text
30
31.global fpsid_read
32.global mvfr0_read
33.global fpscr_read
34.global fpscr_write
35.global fpexc_read
36.global fpexc_write
37
38.global fpu_context_save_s32
39.global fpu_context_restore_s32
40.global fpu_context_save_d16
41.global fpu_context_restore_d16
42.global fpu_context_save_d32
43.global fpu_context_restore_d32
44
45fpsid_read:
46 vmrs r0, fpsid
47 mov pc, lr
48
49mvfr0_read:
50 vmrs r0, mvfr0
51 mov pc, lr
52
53fpscr_read:
54 vmrs r0, fpscr
55 mov pc, lr
56
57fpscr_write:
58 vmsr fpscr, r0
59 mov pc, lr
60
61fpexc_read:
62 vmrs r0, fpexc
63 mov pc, lr
64
65fpexc_write:
66 vmsr fpexc, r0
67 mov pc, lr
68
69fpu_context_save_s32:
70 vmrs r1, fpexc
71 vmrs r2, fpscr
72 stmia r0!, {r1, r2}
73 vstmia r0!, {s0-s31}
74 mov pc, lr
75
76fpu_context_restore_s32:
77 ldmia r0!, {r1, r2}
78 vmsr fpexc, r1
79 vmsr fpscr, r2
80 vldmia r0!, {s0-s31}
81 mov pc, lr
82
83fpu_context_save_d16:
84 vmrs r1, fpexc
85 vmrs r2, fpscr
86 stmia r0!, {r1, r2}
87 vstmia r0!, {d0-d15}
88 mov pc, lr
89
90fpu_context_restore_d16:
91 ldmia r0!, {r1, r2}
92 vmsr fpexc, r1
93 vmsr fpscr, r2
94 vldmia r0!, {d0-d15}
95 mov pc, lr
96
97fpu_context_save_d32:
98 vmrs r1, fpexc
99 stmia r0!, {r1}
100 vmrs r1, fpscr
101 stmia r0!, {r1}
102 vstmia r0!, {d0-d15}
103 vstmia r0!, {d16-d31}
104 mov pc, lr
105
106fpu_context_restore_d32:
107 ldmia r0!, {r1, r2}
108 vmsr fpexc, r1
109 vmsr fpscr, r2
110 vldmia r0!, {d0-d15}
111 vldmia r0!, {d16-d31}
112 mov pc, lr
113
114
115
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