source: mainline/kernel/arch/arm32/src/exception.c@ ba0aa6f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ba0aa6f was 6ac14a70, checked in by Vineeth Pillai <vineethrp@…>, 16 years ago

ARM port for development board integratorcp(ARM926EJ core module).

  • Property mode set to 100644
File size: 5.5 KB
Line 
1/*
2 * Copyright (c) 2007 Petr Stepan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief Exception handlers and exception initialization routines.
34 */
35
36#include <arch/exception.h>
37#include <arch/memstr.h>
38#include <arch/regutils.h>
39#include <interrupt.h>
40#include <arch/mm/page_fault.h>
41#include <arch/barrier.h>
42#include <arch/machine.h>
43#include <print.h>
44#include <syscall/syscall.h>
45
46/** Offset used in calculation of exception handler's relative address.
47 *
48 * @see install_handler()
49 */
50#define PREFETCH_OFFSET 0x8
51
52/** LDR instruction's code */
53#define LDR_OPCODE 0xe59ff000
54
55/** Number of exception vectors. */
56#define EXC_VECTORS 8
57
58/** Size of memory block occupied by exception vectors. */
59#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)
60
61/** Updates specified exception vector to jump to given handler.
62 *
63 * Addresses of handlers are stored in memory following exception vectors.
64 */
65static void install_handler(unsigned handler_addr, unsigned *vector)
66{
67 /* relative address (related to exc. vector) of the word
68 * where handler's address is stored
69 */
70 volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
71 PREFETCH_OFFSET;
72
73 /* make it LDR instruction and store at exception vector */
74 *vector = handler_address_ptr | LDR_OPCODE;
75 smc_coherence(*vector);
76
77 /* store handler's address */
78 *(vector + EXC_VECTORS) = handler_addr;
79
80}
81
82/** Software Interrupt handler.
83 *
84 * Dispatches the syscall.
85 */
86static void swi_exception(int exc_no, istate_t *istate)
87{
88 istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
89 istate->r3, istate->r4, istate->r5, istate->r6);
90}
91
92/** Fills exception vectors with appropriate exception handlers. */
93void install_exception_handlers(void)
94{
95 install_handler((unsigned) reset_exception_entry,
96 (unsigned *) EXC_RESET_VEC);
97
98 install_handler((unsigned) undef_instr_exception_entry,
99 (unsigned *) EXC_UNDEF_INSTR_VEC);
100
101 install_handler((unsigned) swi_exception_entry,
102 (unsigned *) EXC_SWI_VEC);
103
104 install_handler((unsigned) prefetch_abort_exception_entry,
105 (unsigned *) EXC_PREFETCH_ABORT_VEC);
106
107 install_handler((unsigned) data_abort_exception_entry,
108 (unsigned *) EXC_DATA_ABORT_VEC);
109
110 install_handler((unsigned) irq_exception_entry,
111 (unsigned *) EXC_IRQ_VEC);
112
113 install_handler((unsigned) fiq_exception_entry,
114 (unsigned *) EXC_FIQ_VEC);
115}
116
117#ifdef HIGH_EXCEPTION_VECTORS
118/** Activates use of high exception vectors addresses. */
119static void high_vectors(void)
120{
121 uint32_t control_reg;
122
123 asm volatile (
124 "mrc p15, 0, %[control_reg], c1, c1"
125 : [control_reg] "=r" (control_reg)
126 );
127
128 /* switch on the high vectors bit */
129 control_reg |= CP15_R1_HIGH_VECTORS_BIT;
130
131 asm volatile (
132 "mcr p15, 0, %[control_reg], c1, c1"
133 :: [control_reg] "r" (control_reg)
134 );
135}
136#endif
137
138/** Interrupt Exception handler.
139 *
140 * Determines the sources of interrupt and calls their handlers.
141 */
142static void irq_exception(int exc_no, istate_t *istate)
143{
144 machine_irq_exception(exc_no, istate);
145}
146
147/** Initializes exception handling.
148 *
149 * Installs low-level exception handlers and then registers
150 * exceptions and their handlers to kernel exception dispatcher.
151 */
152void exception_init(void)
153{
154#ifdef HIGH_EXCEPTION_VECTORS
155 high_vectors();
156#endif
157 install_exception_handlers();
158
159 exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
160 exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
161 (iroutine) prefetch_abort);
162 exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
163 exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
164}
165
166/** Prints #istate_t structure content.
167 *
168 * @param istate Structure to be printed.
169 */
170void print_istate(istate_t *istate)
171{
172 printf("istate dump:\n");
173
174 printf(" r0: %x r1: %x r2: %x r3: %x\n",
175 istate->r0, istate->r1, istate->r2, istate->r3);
176 printf(" r4: %x r5: %x r6: %x r7: %x\n",
177 istate->r4, istate->r5, istate->r6, istate->r7);
178 printf(" r8: %x r8: %x r10: %x r11: %x\n",
179 istate->r8, istate->r9, istate->r10, istate->r11);
180 printf(" r12: %x sp: %x lr: %x spsr: %x\n",
181 istate->r12, istate->sp, istate->lr, istate->spsr);
182
183 printf(" pc: %x\n", istate->pc);
184}
185
186/** @}
187 */
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