source: mainline/kernel/arch/arm32/src/exception.c@ 22a28a69

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 22a28a69 was 22a28a69, checked in by Jakub Jermar <jakub@…>, 15 years ago

Rename decode_istate() to istate_decode() and declare it only once in
the generic interrupt.h.

  • Property mode set to 100644
File size: 5.6 KB
RevLine 
[6b781c0]1/*
2 * Copyright (c) 2007 Petr Stepan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief Exception handlers and exception initialization routines.
34 */
35
36#include <arch/exception.h>
37#include <arch/memstr.h>
38#include <arch/regutils.h>
[5ac77cc]39#include <arch/machine_func.h>
[6b781c0]40#include <interrupt.h>
41#include <arch/mm/page_fault.h>
[eeaf667]42#include <arch/barrier.h>
[6b781c0]43#include <print.h>
44#include <syscall/syscall.h>
[15817089]45#include <stacktrace.h>
[6b781c0]46
47/** Offset used in calculation of exception handler's relative address.
48 *
49 * @see install_handler()
50 */
51#define PREFETCH_OFFSET 0x8
52
53/** LDR instruction's code */
54#define LDR_OPCODE 0xe59ff000
55
56/** Number of exception vectors. */
57#define EXC_VECTORS 8
58
59/** Size of memory block occupied by exception vectors. */
60#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)
61
62/** Updates specified exception vector to jump to given handler.
63 *
64 * Addresses of handlers are stored in memory following exception vectors.
65 */
[eeaf667]66static void install_handler(unsigned handler_addr, unsigned *vector)
[6b781c0]67{
68 /* relative address (related to exc. vector) of the word
69 * where handler's address is stored
70 */
[9cc0d7c]71 volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
72 PREFETCH_OFFSET;
[6b781c0]73
74 /* make it LDR instruction and store at exception vector */
75 *vector = handler_address_ptr | LDR_OPCODE;
[eeaf667]76 smc_coherence(*vector);
[6b781c0]77
78 /* store handler's address */
79 *(vector + EXC_VECTORS) = handler_addr;
80
81}
82
83/** Software Interrupt handler.
84 *
85 * Dispatches the syscall.
[214ec25c]86 *
[6b781c0]87 */
[214ec25c]88static void swi_exception(unsigned int exc_no, istate_t *istate)
[6b781c0]89{
90 istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
[9cc0d7c]91 istate->r3, istate->r4, istate->r5, istate->r6);
[6b781c0]92}
93
94/** Fills exception vectors with appropriate exception handlers. */
95void install_exception_handlers(void)
96{
97 install_handler((unsigned) reset_exception_entry,
98 (unsigned *) EXC_RESET_VEC);
99
100 install_handler((unsigned) undef_instr_exception_entry,
101 (unsigned *) EXC_UNDEF_INSTR_VEC);
102
103 install_handler((unsigned) swi_exception_entry,
104 (unsigned *) EXC_SWI_VEC);
105
106 install_handler((unsigned) prefetch_abort_exception_entry,
107 (unsigned *) EXC_PREFETCH_ABORT_VEC);
108
109 install_handler((unsigned) data_abort_exception_entry,
110 (unsigned *) EXC_DATA_ABORT_VEC);
111
112 install_handler((unsigned) irq_exception_entry,
113 (unsigned *) EXC_IRQ_VEC);
114
[00287cc]115 install_handler((unsigned) fiq_exception_entry,
[6b781c0]116 (unsigned *) EXC_FIQ_VEC);
117}
118
119#ifdef HIGH_EXCEPTION_VECTORS
120/** Activates use of high exception vectors addresses. */
121static void high_vectors(void)
122{
123 uint32_t control_reg;
124
[e762b43]125 asm volatile (
126 "mrc p15, 0, %[control_reg], c1, c1"
127 : [control_reg] "=r" (control_reg)
128 );
[6b781c0]129
130 /* switch on the high vectors bit */
131 control_reg |= CP15_R1_HIGH_VECTORS_BIT;
132
[e762b43]133 asm volatile (
134 "mcr p15, 0, %[control_reg], c1, c1"
135 :: [control_reg] "r" (control_reg)
136 );
[6b781c0]137}
138#endif
139
[6ac14a70]140/** Interrupt Exception handler.
141 *
142 * Determines the sources of interrupt and calls their handlers.
143 */
[214ec25c]144static void irq_exception(unsigned int exc_no, istate_t *istate)
[6ac14a70]145{
146 machine_irq_exception(exc_no, istate);
147}
148
[6b781c0]149/** Initializes exception handling.
[e762b43]150 *
[6b781c0]151 * Installs low-level exception handlers and then registers
152 * exceptions and their handlers to kernel exception dispatcher.
153 */
154void exception_init(void)
155{
156#ifdef HIGH_EXCEPTION_VECTORS
157 high_vectors();
158#endif
159 install_exception_handlers();
160
[b3b7e14a]161 exc_register(EXC_IRQ, "interrupt", true,
162 (iroutine_t) irq_exception);
163 exc_register(EXC_PREFETCH_ABORT, "prefetch abort", true,
164 (iroutine_t) prefetch_abort);
165 exc_register(EXC_DATA_ABORT, "data abort", true,
166 (iroutine_t) data_abort);
167 exc_register(EXC_SWI, "software interrupt", true,
168 (iroutine_t) swi_exception);
[6b781c0]169}
170
171/** Prints #istate_t structure content.
172 *
173 * @param istate Structure to be printed.
174 */
[22a28a69]175void istate_decode(istate_t *istate)
[6b781c0]176{
[8e374ea7]177 printf("r0 =%#0.8lx\tr1 =%#0.8lx\tr2 =%#0.8lx\tr3 =%#0.8lx\n",
[6b781c0]178 istate->r0, istate->r1, istate->r2, istate->r3);
[8e374ea7]179 printf("r4 =%#0.8lx\tr5 =%#0.8lx\tr6 =%#0.8lx\tr7 =%#0.8lx\n",
[6b781c0]180 istate->r4, istate->r5, istate->r6, istate->r7);
[8e374ea7]181 printf("r8 =%#0.8lx\tr9 =%#0.8lx\tr10=%#0.8lx\tfp =%#0.8lx\n",
[83c5973]182 istate->r8, istate->r9, istate->r10, istate->fp);
[8e374ea7]183 printf("r12=%#0.8lx\tsp =%#0.8lx\tlr =%#0.8lx\tspsr=%#0.8lx\n",
[6b781c0]184 istate->r12, istate->sp, istate->lr, istate->spsr);
185}
186
187/** @}
188 */
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