source: mainline/kernel/arch/arm32/src/exc_handler.S@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was a5f63cd, checked in by Jakub Jermar <jakub@…>, 15 years ago

Stop tracing arm32 stacks on the exception boundary.

For arm32, it would actually be easy to enable tracing
nested exceptions, because the register-save code already
makes a distinction whether the interrupted context is
user or kernel. We do not enable it right now just to
be consistent with the other architectures.

  • Property mode set to 100644
File size: 4.6 KB
Line 
1#
2# Copyright (c) 2009 Vineeth Pillai
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29.text
30
31.global irq_exception_entry
32.global fiq_exception_entry
33.global data_abort_exception_entry
34.global prefetch_abort_exception_entry
35.global undef_instr_exception_entry
36.global swi_exception_entry
37.global reset_exception_entry
38
39
40# Switches to kernel stack and saves all registers there.
41#
42# The stack frame created by the function looks like:
43#
44# |_________________|
45# | |
46# | SPSR |
47# | |
48# |_________________|
49# | Stack Pointer |
50# | of |
51# | Previous Mode |
52# |_________________|
53# | Return address |
54# | of |
55# | Previous Mode |
56# |_________________|
57# | R0 - R12 |
58# | of |
59# | Previous Mode |
60# |_________________|
61# | Return address |
62# | from |
63# |Exception Handler|
64# |_________________|
65# | |
66#
67#
68
69.macro SAVE_REGS_TO_STACK
70 stmfd r13!, {r0-r3}
71 mov r3, sp
72 add sp, sp, #16
73 mrs r1, cpsr
74 bic r1, r1, #0x1f
75 mrs r2, spsr
76 and r0, r2, #0x1f
77 cmp r0, #0x10
78 bne 1f
79
80 # prev mode was usermode
81 mov r0, lr
82
83 # Switch to supervisor mode
84 orr r1, r1, #0x13
85 msr cpsr_c, r1
86
87 # Load sp with [supervisor_sp]
88 ldr r13, =supervisor_sp
89 ldr r13, [r13]
90
91 # Populate the stack frame
92 msr spsr, r2
93 mov lr, r0
94 stmfd r13!, {lr}
95 stmfd r13!, {r4-r12}
96 ldmfd r3!, {r4-r7}
97 stmfd r13!, {r4-r7}
98 stmfd r13!, {r13, lr}^
99 stmfd r13!, {r2}
100 b 2f
101
102 # mode was not usermode
1031:
104 # Switch to previous mode which is undoubtedly the supervisor mode
105 orr r1, r1, r0
106 mov r0, lr
107 msr cpsr_c, r1
108
109 # Populate the stack frame
110 mov r1, sp
111 stmfd r13!, {r0}
112 stmfd r13!, {r4-r12}
113
114 # Store r0-r3 in r4-r7 and then push it on to stack
115 ldmfd r3!, {r4-r7}
116 stmfd r13!, {r4-r7}
117
118 # Push return address and stack pointer on to stack
119 stmfd r13!, {lr}
120 stmfd r13!, {r1}
121 mov lr, r0
122 msr spsr, r2
123 stmfd r13!, {r2}
1242:
125 # Stop stack traces here
126 mov fp, #0
127.endm
128
129.macro LOAD_REGS_FROM_STACK
130 ldmfd r13!, {r0}
131 msr spsr, r0
132 and r0, r0, #0x1f
133 cmp r0, #0x10
134 bne 1f
135
136 # return to user mode
137 ldmfd r13!, {r13, lr}^
138 b 2f
139
140 # return to non-user mode
1411:
142 ldmfd r13!, {r1, lr}
143
1442:
145 ldmfd r13!, {r0-r12, pc}^
146.endm
147
148reset_exception_entry:
149 SAVE_REGS_TO_STACK
150 mov r0, #0
151 mov r1, r13
152 bl ras_check
153 LOAD_REGS_FROM_STACK
154
155irq_exception_entry:
156 sub lr, lr, #4
157 SAVE_REGS_TO_STACK
158 mov r0, #5
159 mov r1, r13
160 bl ras_check
161 LOAD_REGS_FROM_STACK
162
163fiq_exception_entry:
164 sub lr, lr, #4
165 SAVE_REGS_TO_STACK
166 mov r0, #6
167 mov r1, r13
168 bl ras_check
169 LOAD_REGS_FROM_STACK
170
171undef_instr_exception_entry:
172 SAVE_REGS_TO_STACK
173 mov r0, #1
174 mov r1, r13
175 bl ras_check
176 LOAD_REGS_FROM_STACK
177
178prefetch_abort_exception_entry:
179 sub lr, lr, #4
180 SAVE_REGS_TO_STACK
181 mov r0, #3
182 mov r1, r13
183 bl ras_check
184 LOAD_REGS_FROM_STACK
185
186data_abort_exception_entry:
187 sub lr, lr, #8
188 SAVE_REGS_TO_STACK
189 mov r0, #4
190 mov r1, r13
191 bl ras_check
192 LOAD_REGS_FROM_STACK
193
194swi_exception_entry:
195 ldr r13, =exc_stack
196 SAVE_REGS_TO_STACK
197 mov r0, #2
198 mov r1, r13
199 bl ras_check
200 LOAD_REGS_FROM_STACK
201
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