source: mainline/kernel/arch/arm32/src/exc_handler.S@ 7cf3e66

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7cf3e66 was 8e374ea7, checked in by Jakub Jermar <jakub@…>, 15 years ago

Switch arm32 to use the unified panic architecture.

  • Property mode set to 100644
File size: 4.6 KB
RevLine 
[6ac14a70]1#
2# Copyright (c) 2009 Vineeth Pillai
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29.text
30
31.global irq_exception_entry
32.global fiq_exception_entry
33.global data_abort_exception_entry
34.global prefetch_abort_exception_entry
35.global undef_instr_exception_entry
36.global swi_exception_entry
37.global reset_exception_entry
38
39
40# Switches to kernel stack and saves all registers there.
41#
42# The stack frame created by the function looks like:
43#
44# |_________________|
45# | |
46# | SPSR |
47# | |
48# |_________________|
49# | Stack Pointer |
50# | of |
51# | Previous Mode |
52# |_________________|
53# | Return address |
54# | of |
55# | Previous Mode |
56# |_________________|
57# | R0 - R12 |
58# | of |
59# | Previous Mode |
60# |_________________|
61# | Return address |
62# | from |
63# |Exception Handler|
64# |_________________|
65# | |
66#
67#
68
69.macro SAVE_REGS_TO_STACK
70 stmfd r13!, {r0-r3}
71 mov r3, sp
72 add sp, sp, #16
73 mrs r1, cpsr
74 bic r1, r1, #0x1f
75 mrs r2, spsr
76 and r0, r2, #0x1f
77 cmp r0, #0x10
78 bne 1f
79
80 # prev mode was usermode
81 mov r0, lr
82
83 # Switch to supervisor mode
84 orr r1, r1, #0x13
85 msr cpsr_c, r1
86
87 # Load sp with [supervisor_sp]
88 ldr r13, =supervisor_sp
89 ldr r13, [r13]
90
91 # Populate the stack frame
92 msr spsr, r2
93 mov lr, r0
94 stmfd r13!, {lr}
95 stmfd r13!, {r4-r12}
96 ldmfd r3!, {r4-r7}
97 stmfd r13!, {r4-r7}
98 stmfd r13!, {r13, lr}^
99 stmfd r13!, {r2}
[8e374ea7]100
101 # Stop stack traces here
102 mov fp, #0
103
[6ac14a70]104 b 2f
105
106 # mode was not usermode
1071:
108 # Switch to previous mode which is undoubtedly the supervisor mode
109 orr r1, r1, r0
110 mov r0, lr
111 msr cpsr_c, r1
112
113 # Populate the stack frame
114 mov r1, sp
115 stmfd r13!, {r0}
116 stmfd r13!, {r4-r12}
117
118 # Store r0-r3 in r4-r7 and then push it on to stack
119 ldmfd r3!, {r4-r7}
120 stmfd r13!, {r4-r7}
121
122 # Push return address and stack pointer on to stack
123 stmfd r13!, {lr}
124 stmfd r13!, {r1}
125 mov lr, r0
126 msr spsr, r2
127 stmfd r13!, {r2}
1282:
129.endm
130
131.macro LOAD_REGS_FROM_STACK
132 ldmfd r13!, {r0}
133 msr spsr, r0
134 and r0, r0, #0x1f
135 cmp r0, #0x10
136 bne 1f
137
138 # return to user mode
139 ldmfd r13!, {r13, lr}^
140 b 2f
141
142 # return to non-user mode
1431:
144 ldmfd r13!, {r1, lr}
145
1462:
147 ldmfd r13!, {r0-r12, pc}^
148.endm
149
150reset_exception_entry:
151 SAVE_REGS_TO_STACK
152 mov r0, #0
153 mov r1, r13
[b3b7e14a]154 bl ras_check
[6ac14a70]155 LOAD_REGS_FROM_STACK
156
157irq_exception_entry:
158 sub lr, lr, #4
159 SAVE_REGS_TO_STACK
160 mov r0, #5
161 mov r1, r13
[b3b7e14a]162 bl ras_check
[6ac14a70]163 LOAD_REGS_FROM_STACK
164
165fiq_exception_entry:
166 sub lr, lr, #4
167 SAVE_REGS_TO_STACK
168 mov r0, #6
169 mov r1, r13
[b3b7e14a]170 bl ras_check
[6ac14a70]171 LOAD_REGS_FROM_STACK
172
173undef_instr_exception_entry:
174 SAVE_REGS_TO_STACK
175 mov r0, #1
176 mov r1, r13
[b3b7e14a]177 bl ras_check
[6ac14a70]178 LOAD_REGS_FROM_STACK
179
180prefetch_abort_exception_entry:
181 sub lr, lr, #4
182 SAVE_REGS_TO_STACK
183 mov r0, #3
184 mov r1, r13
[b3b7e14a]185 bl ras_check
[6ac14a70]186 LOAD_REGS_FROM_STACK
187
188data_abort_exception_entry:
189 sub lr, lr, #8
190 SAVE_REGS_TO_STACK
191 mov r0, #4
192 mov r1, r13
[b3b7e14a]193 bl ras_check
[6ac14a70]194 LOAD_REGS_FROM_STACK
195
196swi_exception_entry:
197 ldr r13, =exc_stack
198 SAVE_REGS_TO_STACK
199 mov r0, #2
200 mov r1, r13
[82a04c6]201 bl ras_check
[6ac14a70]202 LOAD_REGS_FROM_STACK
203
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