source: mainline/kernel/arch/arm32/src/cpu/cpu.c@ d5ed54b

serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d5ed54b was bab75df6, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Let kernel code get printf via the standard stdio header. Clean up unused includes.
  • Property mode set to 100644
File size: 10.5 KB
Line 
1/*
2 * Copyright (c) 2007 Michal Kebrt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_arm32
30 * @{
31 */
32/** @file
33 * @brief CPU identification.
34 */
35
36#include <arch/cache.h>
37#include <arch/cpu.h>
38#include <arch/cp15.h>
39#include <cpu.h>
40#include <arch.h>
41#include <stdio.h>
42
43#ifdef CONFIG_FPU
44#include <arch/fpu_context.h>
45#endif
46
47static inline unsigned log2(unsigned val)
48{
49 unsigned log = 0;
50 --val;
51 while (val) {
52 ++log;
53 val >>= 1;
54 }
55 return log;
56}
57
58static unsigned dcache_ways(unsigned level);
59static unsigned dcache_sets(unsigned level);
60static unsigned dcache_linesize_log(unsigned level);
61
62/** Implementers (vendor) names */
63static const char *implementer(unsigned id)
64{
65 switch (id) {
66 case 0x41:
67 return "ARM Limited";
68 case 0x44:
69 return "Digital Equipment Corporation";
70 case 0x4d:
71 return "Motorola, Freescale Semiconductor Inc.";
72 case 0x51:
73 return "Qualcomm Inc.";
74 case 0x56:
75 return "Marvell Semiconductor Inc.";
76 case 0x69:
77 return "Intel Corporation";
78 }
79 return "Unknown implementer";
80}
81
82/** Architecture names */
83static const char *architecture_string(cpu_arch_t *arch)
84{
85 static const char *arch_data[] = {
86 "ARM", /* 0x0 */
87 "ARMv4", /* 0x1 */
88 "ARMv4T", /* 0x2 */
89 "ARMv5", /* 0x3 */
90 "ARMv5T", /* 0x4 */
91 "ARMv5TE", /* 0x5 */
92 "ARMv5TEJ", /* 0x6 */
93 "ARMv6" /* 0x7 */
94 };
95 if (arch->arch_num < (sizeof(arch_data) / sizeof(arch_data[0])))
96 return arch_data[arch->arch_num];
97 else
98 return arch_data[0];
99}
100
101/** Retrieves processor identification from CP15 register 0.
102 *
103 * @param cpu Structure for storing CPU identification.
104 * See page B4-1630 of ARM Architecture Reference Manual.
105 */
106static void arch_cpu_identify(cpu_arch_t *cpu)
107{
108 const uint32_t ident = MIDR_read();
109
110 cpu->imp_num = (ident >> MIDR_IMPLEMENTER_SHIFT) & MIDR_IMPLEMENTER_MASK;
111 cpu->variant_num = (ident >> MIDR_VARIANT_SHIFT) & MIDR_VARIANT_MASK;
112 cpu->arch_num = (ident >> MIDR_ARCHITECTURE_SHIFT) & MIDR_ARCHITECTURE_MASK;
113 cpu->prim_part_num = (ident >> MIDR_PART_NUMBER_SHIFT) & MIDR_PART_NUMBER_MASK;
114 cpu->rev_num = (ident >> MIDR_REVISION_SHIFT) & MIDR_REVISION_MASK;
115
116 // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
117 cpu->dcache_levels = dcache_levels();
118
119 for (unsigned i = 0; i < cpu->dcache_levels; ++i) {
120 cpu->dcache[i].ways = dcache_ways(i);
121 cpu->dcache[i].sets = dcache_sets(i);
122 cpu->dcache[i].way_shift = 31 - log2(cpu->dcache[i].ways);
123 cpu->dcache[i].set_shift = dcache_linesize_log(i);
124 cpu->dcache[i].line_size = 1 << dcache_linesize_log(i);
125 printf("Found DCache L%u: %u-way, %u sets, %u byte lines "
126 "(shifts: w%u, s%u)\n", i + 1, cpu->dcache[i].ways,
127 cpu->dcache[i].sets, cpu->dcache[i].line_size,
128 cpu->dcache[i].way_shift, cpu->dcache[i].set_shift);
129 }
130}
131
132/** Enables unaligned access and caching for armv6+ */
133void cpu_arch_init(void)
134{
135 uint32_t control_reg = SCTLR_read();
136
137 dcache_invalidate();
138 read_barrier();
139
140 /* Turn off tex remap, RAZ/WI prior to armv7 */
141 control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
142 /* Turn off accessed flag, RAZ/WI prior to armv7 */
143 control_reg &= ~(SCTLR_ACCESS_FLAG_EN_FLAG | SCTLR_HW_ACCESS_FLAG_EN_FLAG);
144
145 /* Unaligned access is supported on armv6+ */
146#if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
147 /*
148 * Enable unaligned access, RAZ/WI prior to armv6
149 * switchable on armv6, RAO/WI writes on armv7,
150 * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
151 * L.3.1 (p. 2456)
152 */
153 control_reg |= SCTLR_UNALIGNED_EN_FLAG;
154 /*
155 * Disable alignment checks, this turns unaligned access to undefined,
156 * unless U bit is set.
157 */
158 control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
159 /*
160 * Enable caching, On arm prior to armv7 there is only one level
161 * of caches. Data cache is coherent.
162 * "This means that the behavior of accesses from the same observer to
163 * different VAs, that are translated to the same PA
164 * with the same memory attributes, is fully coherent."
165 * ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
166 * B3.11.1 (p. 1383)
167 * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
168 * L2 Cache for armv7 is enabled by default (i.e. controlled by
169 * this flag).
170 */
171 control_reg |= SCTLR_CACHE_EN_FLAG;
172#endif
173#ifdef PROCESSOR_ARCH_armv7_a
174 /*
175 * ICache coherency is elaborated on in barrier.h.
176 * VIPT and PIPT caches need maintenance only on code modify,
177 * so it should be safe for general use.
178 * Enable branch predictors too as they follow the same rules
179 * as ICache and they can be flushed together
180 */
181 if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) {
182 control_reg |=
183 SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
184 } else {
185 control_reg &=
186 ~(SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG);
187 }
188#endif
189 SCTLR_write(control_reg);
190
191#ifdef CONFIG_FPU
192 fpu_setup();
193#endif
194
195#ifdef PROCESSOR_ARCH_armv7_a
196 if ((ID_PFR1_read() & ID_PFR1_GEN_TIMER_EXT_MASK) !=
197 ID_PFR1_GEN_TIMER_EXT) {
198 PMCR_write(PMCR_read() | PMCR_E_FLAG | PMCR_D_FLAG);
199 PMCNTENSET_write(PMCNTENSET_CYCLE_COUNTER_EN_FLAG);
200 }
201#endif
202}
203
204/** Retrieves processor identification and stores it to #CPU.arch */
205void cpu_identify(void)
206{
207 arch_cpu_identify(&CPU->arch);
208}
209
210/** Prints CPU identification. */
211void cpu_print_report(cpu_t *m)
212{
213 printf("cpu%d: vendor=%s, architecture=%s, part number=%x, "
214 "variant=%x, revision=%x\n",
215 m->id, implementer(m->arch.imp_num),
216 architecture_string(&m->arch), m->arch.prim_part_num,
217 m->arch.variant_num, m->arch.rev_num);
218}
219
220/** See chapter B4.1.19 of ARM Architecture Reference Manual */
221static unsigned dcache_linesize_log(unsigned level)
222{
223#ifdef PROCESSOR_ARCH_armv7_a
224 CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
225 const uint32_t ccsidr = CCSIDR_read();
226 return CCSIDR_LINESIZE_LOG(ccsidr);
227#endif
228 return 0;
229
230}
231
232/** See chapter B4.1.19 of ARM Architecture Reference Manual */
233static unsigned dcache_ways(unsigned level)
234{
235#ifdef PROCESSOR_ARCH_armv7_a
236 CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
237 const uint32_t ccsidr = CCSIDR_read();
238 return CCSIDR_WAYS(ccsidr);
239#endif
240 return 0;
241}
242
243/** See chapter B4.1.19 of ARM Architecture Reference Manual */
244static unsigned dcache_sets(unsigned level)
245{
246#ifdef PROCESSOR_ARCH_armv7_a
247 CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
248 const uint32_t ccsidr = CCSIDR_read();
249 return CCSIDR_SETS(ccsidr);
250#endif
251 return 0;
252}
253
254unsigned dcache_levels(void)
255{
256 unsigned levels = 0;
257#ifdef PROCESSOR_ARCH_armv7_a
258 const uint32_t val = CLIDR_read();
259 for (unsigned i = 0; i < 8; ++i) {
260 const unsigned ctype = CLIDR_CACHE(i, val);
261 switch (ctype) {
262 case CLIDR_DCACHE_ONLY:
263 case CLIDR_SEP_CACHE:
264 case CLIDR_UNI_CACHE:
265 ++levels;
266 default:
267 (void)0;
268 }
269 }
270#endif
271 return levels;
272}
273
274static void dcache_clean_manual(unsigned level, bool invalidate,
275 unsigned ways, unsigned sets, unsigned way_shift, unsigned set_shift)
276{
277
278 for (unsigned i = 0; i < ways; ++i) {
279 for (unsigned j = 0; j < sets; ++j) {
280 const uint32_t val =
281 ((level & 0x7) << 1) |
282 (j << set_shift) | (i << way_shift);
283 if (invalidate)
284 DCCISW_write(val);
285 else
286 DCCSW_write(val);
287 }
288 }
289}
290
291void dcache_flush(void)
292{
293 /* See ARM Architecture Reference Manual ch. B4.2.1 p. B4-1724 */
294 const unsigned levels = dcache_levels();
295 for (unsigned i = 0; i < levels; ++i) {
296 const unsigned ways = dcache_ways(i);
297 const unsigned sets = dcache_sets(i);
298 const unsigned way_shift = 32 - log2(ways);
299 const unsigned set_shift = dcache_linesize_log(i);
300 dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
301 }
302}
303
304void dcache_flush_invalidate(void)
305{
306 /* See ARM Architecture Reference Manual ch. B4.2.1 p. B4-1724 */
307 const unsigned levels = dcache_levels();
308 for (unsigned i = 0; i < levels; ++i) {
309 const unsigned ways = dcache_ways(i);
310 const unsigned sets = dcache_sets(i);
311 const unsigned way_shift = 32 - log2(ways);
312 const unsigned set_shift = dcache_linesize_log(i);
313 dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);
314 }
315}
316
317void cpu_dcache_flush(void)
318{
319 for (unsigned i = 0; i < CPU->arch.dcache_levels; ++i)
320 dcache_clean_manual(i, false,
321 CPU->arch.dcache[i].ways, CPU->arch.dcache[i].sets,
322 CPU->arch.dcache[i].way_shift, CPU->arch.dcache[i].set_shift);
323}
324
325void cpu_dcache_flush_invalidate(void)
326{
327 const unsigned levels = dcache_levels();
328 for (unsigned i = 0; i < levels; ++i)
329 dcache_clean_manual(i, true,
330 CPU->arch.dcache[i].ways, CPU->arch.dcache[i].sets,
331 CPU->arch.dcache[i].way_shift, CPU->arch.dcache[i].set_shift);
332}
333
334void icache_invalidate(void)
335{
336#if defined(PROCESSOR_ARCH_armv7_a)
337 ICIALLU_write(0);
338#else
339 ICIALL_write(0);
340#endif
341}
342
343#if !defined(PROCESSOR_ARCH_armv7_a)
344static bool cache_is_unified(void)
345{
346 if (MIDR_read() != CTR_read()) {
347 /* We have the CTR register */
348 return (CTR_read() & CTR_SEP_FLAG) != CTR_SEP_FLAG;
349 } else {
350 panic("Unknown cache type");
351 }
352}
353#endif
354
355void dcache_invalidate(void)
356{
357#if defined(PROCESSOR_ARCH_armv7_a)
358 dcache_flush_invalidate();
359#else
360 if (cache_is_unified())
361 CIALL_write(0);
362 else
363 DCIALL_write(0);
364#endif
365}
366
367void dcache_clean_mva_pou(uintptr_t mva)
368{
369#if defined(PROCESSOR_ARCH_armv7_a)
370 DCCMVAU_write(mva);
371#else
372 if (cache_is_unified())
373 CCMVA_write(mva);
374 else
375 DCCMVA_write(mva);
376#endif
377}
378
379/** @}
380 */
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