source: mainline/kernel/arch/arm32/src/cpu/cpu.c@ 11b285d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 11b285d was ae7d03c, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Selected ccheck-proposed comment fixes.
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1/*
2 * Copyright (c) 2007 Michal Kebrt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief CPU identification.
34 */
35
36#include <arch/cache.h>
37#include <arch/cpu.h>
38#include <arch/cp15.h>
39#include <cpu.h>
40#include <arch.h>
41#include <print.h>
42
43#ifdef CONFIG_FPU
44#include <arch/fpu_context.h>
45#endif
46
47static inline unsigned log2(unsigned val)
48{
49 unsigned log = 0;
50 --val;
51 while (val) {
52 ++log;
53 val >>= 1;
54 }
55 return log;
56}
57
58static unsigned dcache_ways(unsigned level);
59static unsigned dcache_sets(unsigned level);
60static unsigned dcache_linesize_log(unsigned level);
61
62
63/** Implementers (vendor) names */
64static const char *implementer(unsigned id)
65{
66 switch (id) {
67 case 0x41:
68 return "ARM Limited";
69 case 0x44:
70 return "Digital Equipment Corporation";
71 case 0x4d:
72 return "Motorola, Freescale Semiconductor Inc.";
73 case 0x51:
74 return "Qualcomm Inc.";
75 case 0x56:
76 return "Marvell Semiconductor Inc.";
77 case 0x69:
78 return "Intel Corporation";
79 }
80 return "Unknown implementer";
81}
82
83/** Architecture names */
84static const char *architecture_string(cpu_arch_t *arch)
85{
86 static const char *arch_data[] = {
87 "ARM", /* 0x0 */
88 "ARMv4", /* 0x1 */
89 "ARMv4T", /* 0x2 */
90 "ARMv5", /* 0x3 */
91 "ARMv5T", /* 0x4 */
92 "ARMv5TE", /* 0x5 */
93 "ARMv5TEJ", /* 0x6 */
94 "ARMv6" /* 0x7 */
95 };
96 if (arch->arch_num < (sizeof(arch_data) / sizeof(arch_data[0])))
97 return arch_data[arch->arch_num];
98 else
99 return arch_data[0];
100}
101
102
103/** Retrieves processor identification from CP15 register 0.
104 *
105 * @param cpu Structure for storing CPU identification.
106 * See page B4-1630 of ARM Architecture Reference Manual.
107 */
108static void arch_cpu_identify(cpu_arch_t *cpu)
109{
110 const uint32_t ident = MIDR_read();
111
112 cpu->imp_num = (ident >> MIDR_IMPLEMENTER_SHIFT) & MIDR_IMPLEMENTER_MASK;
113 cpu->variant_num = (ident >> MIDR_VARIANT_SHIFT) & MIDR_VARIANT_MASK;
114 cpu->arch_num = (ident >> MIDR_ARCHITECTURE_SHIFT) & MIDR_ARCHITECTURE_MASK;
115 cpu->prim_part_num = (ident >> MIDR_PART_NUMBER_SHIFT) & MIDR_PART_NUMBER_MASK;
116 cpu->rev_num = (ident >> MIDR_REVISION_SHIFT) & MIDR_REVISION_MASK;
117
118 // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
119 cpu->dcache_levels = dcache_levels();
120
121 for (unsigned i = 0; i < cpu->dcache_levels; ++i) {
122 cpu->dcache[i].ways = dcache_ways(i);
123 cpu->dcache[i].sets = dcache_sets(i);
124 cpu->dcache[i].way_shift = 31 - log2(cpu->dcache[i].ways);
125 cpu->dcache[i].set_shift = dcache_linesize_log(i);
126 cpu->dcache[i].line_size = 1 << dcache_linesize_log(i);
127 printf("Found DCache L%u: %u-way, %u sets, %u byte lines "
128 "(shifts: w%u, s%u)\n", i + 1, cpu->dcache[i].ways,
129 cpu->dcache[i].sets, cpu->dcache[i].line_size,
130 cpu->dcache[i].way_shift, cpu->dcache[i].set_shift);
131 }
132}
133
134/** Enables unaligned access and caching for armv6+ */
135void cpu_arch_init(void)
136{
137 uint32_t control_reg = SCTLR_read();
138
139 dcache_invalidate();
140 read_barrier();
141
142 /* Turn off tex remap, RAZ/WI prior to armv7 */
143 control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
144 /* Turn off accessed flag, RAZ/WI prior to armv7 */
145 control_reg &= ~(SCTLR_ACCESS_FLAG_EN_FLAG | SCTLR_HW_ACCESS_FLAG_EN_FLAG);
146
147 /* Unaligned access is supported on armv6+ */
148#if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
149 /* Enable unaligned access, RAZ/WI prior to armv6
150 * switchable on armv6, RAO/WI writes on armv7,
151 * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
152 * L.3.1 (p. 2456) */
153 control_reg |= SCTLR_UNALIGNED_EN_FLAG;
154 /* Disable alignment checks, this turns unaligned access to undefined,
155 * unless U bit is set. */
156 control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
157 /* Enable caching, On arm prior to armv7 there is only one level
158 * of caches. Data cache is coherent.
159 * "This means that the behavior of accesses from the same observer to
160 * different VAs, that are translated to the same PA
161 * with the same memory attributes, is fully coherent."
162 * ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
163 * B3.11.1 (p. 1383)
164 * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
165 * L2 Cache for armv7 is enabled by default (i.e. controlled by
166 * this flag).
167 */
168 control_reg |= SCTLR_CACHE_EN_FLAG;
169#endif
170#ifdef PROCESSOR_ARCH_armv7_a
171 /* ICache coherency is elaborated on in barrier.h.
172 * VIPT and PIPT caches need maintenance only on code modify,
173 * so it should be safe for general use.
174 * Enable branch predictors too as they follow the same rules
175 * as ICache and they can be flushed together
176 */
177 if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) {
178 control_reg |=
179 SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
180 } else {
181 control_reg &=
182 ~(SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG);
183 }
184#endif
185 SCTLR_write(control_reg);
186
187#ifdef CONFIG_FPU
188 fpu_setup();
189#endif
190
191#ifdef PROCESSOR_ARCH_armv7_a
192 if ((ID_PFR1_read() & ID_PFR1_GEN_TIMER_EXT_MASK) !=
193 ID_PFR1_GEN_TIMER_EXT) {
194 PMCR_write(PMCR_read() | PMCR_E_FLAG | PMCR_D_FLAG);
195 PMCNTENSET_write(PMCNTENSET_CYCLE_COUNTER_EN_FLAG);
196 }
197#endif
198}
199
200/** Retrieves processor identification and stores it to #CPU.arch */
201void cpu_identify(void)
202{
203 arch_cpu_identify(&CPU->arch);
204}
205
206/** Prints CPU identification. */
207void cpu_print_report(cpu_t *m)
208{
209 printf("cpu%d: vendor=%s, architecture=%s, part number=%x, "
210 "variant=%x, revision=%x\n",
211 m->id, implementer(m->arch.imp_num),
212 architecture_string(&m->arch), m->arch.prim_part_num,
213 m->arch.variant_num, m->arch.rev_num);
214}
215
216/** See chapter B4.1.19 of ARM Architecture Reference Manual */
217static unsigned dcache_linesize_log(unsigned level)
218{
219#ifdef PROCESSOR_ARCH_armv7_a
220 CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
221 const uint32_t ccsidr = CCSIDR_read();
222 return CCSIDR_LINESIZE_LOG(ccsidr);
223#endif
224 return 0;
225
226}
227
228/** See chapter B4.1.19 of ARM Architecture Reference Manual */
229static unsigned dcache_ways(unsigned level)
230{
231#ifdef PROCESSOR_ARCH_armv7_a
232 CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
233 const uint32_t ccsidr = CCSIDR_read();
234 return CCSIDR_WAYS(ccsidr);
235#endif
236 return 0;
237}
238
239/** See chapter B4.1.19 of ARM Architecture Reference Manual */
240static unsigned dcache_sets(unsigned level)
241{
242#ifdef PROCESSOR_ARCH_armv7_a
243 CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
244 const uint32_t ccsidr = CCSIDR_read();
245 return CCSIDR_SETS(ccsidr);
246#endif
247 return 0;
248}
249
250unsigned dcache_levels(void)
251{
252 unsigned levels = 0;
253#ifdef PROCESSOR_ARCH_armv7_a
254 const uint32_t val = CLIDR_read();
255 for (unsigned i = 0; i < 8; ++i) {
256 const unsigned ctype = CLIDR_CACHE(i, val);
257 switch (ctype) {
258 case CLIDR_DCACHE_ONLY:
259 case CLIDR_SEP_CACHE:
260 case CLIDR_UNI_CACHE:
261 ++levels;
262 default:
263 (void)0;
264 }
265 }
266#endif
267 return levels;
268}
269
270static void dcache_clean_manual(unsigned level, bool invalidate,
271 unsigned ways, unsigned sets, unsigned way_shift, unsigned set_shift)
272{
273
274 for (unsigned i = 0; i < ways; ++i) {
275 for (unsigned j = 0; j < sets; ++j) {
276 const uint32_t val =
277 ((level & 0x7) << 1) |
278 (j << set_shift) | (i << way_shift);
279 if (invalidate)
280 DCCISW_write(val);
281 else
282 DCCSW_write(val);
283 }
284 }
285}
286
287void dcache_flush(void)
288{
289 /* See ARM Architecture Reference Manual ch. B4.2.1 p. B4-1724 */
290 const unsigned levels = dcache_levels();
291 for (unsigned i = 0; i < levels; ++i) {
292 const unsigned ways = dcache_ways(i);
293 const unsigned sets = dcache_sets(i);
294 const unsigned way_shift = 32 - log2(ways);
295 const unsigned set_shift = dcache_linesize_log(i);
296 dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
297 }
298}
299
300void dcache_flush_invalidate(void)
301{
302 /* See ARM Architecture Reference Manual ch. B4.2.1 p. B4-1724 */
303 const unsigned levels = dcache_levels();
304 for (unsigned i = 0; i < levels; ++i) {
305 const unsigned ways = dcache_ways(i);
306 const unsigned sets = dcache_sets(i);
307 const unsigned way_shift = 32 - log2(ways);
308 const unsigned set_shift = dcache_linesize_log(i);
309 dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);
310 }
311}
312
313
314void cpu_dcache_flush(void)
315{
316 for (unsigned i = 0; i < CPU->arch.dcache_levels; ++i)
317 dcache_clean_manual(i, false,
318 CPU->arch.dcache[i].ways, CPU->arch.dcache[i].sets,
319 CPU->arch.dcache[i].way_shift, CPU->arch.dcache[i].set_shift);
320}
321
322void cpu_dcache_flush_invalidate(void)
323{
324 const unsigned levels = dcache_levels();
325 for (unsigned i = 0; i < levels; ++i)
326 dcache_clean_manual(i, true,
327 CPU->arch.dcache[i].ways, CPU->arch.dcache[i].sets,
328 CPU->arch.dcache[i].way_shift, CPU->arch.dcache[i].set_shift);
329}
330
331void icache_invalidate(void)
332{
333#if defined(PROCESSOR_ARCH_armv7_a)
334 ICIALLU_write(0);
335#else
336 ICIALL_write(0);
337#endif
338}
339
340#if !defined(PROCESSOR_ARCH_armv7_a)
341static bool cache_is_unified(void)
342{
343 if (MIDR_read() != CTR_read()) {
344 /* We have the CTR register */
345 return (CTR_read() & CTR_SEP_FLAG) != CTR_SEP_FLAG;
346 } else {
347 panic("Unknown cache type");
348 }
349}
350#endif
351
352void dcache_invalidate(void)
353{
354#if defined(PROCESSOR_ARCH_armv7_a)
355 dcache_flush_invalidate();
356#else
357 if (cache_is_unified())
358 CIALL_write(0);
359 else
360 DCIALL_write(0);
361#endif
362}
363
364void dcache_clean_mva_pou(uintptr_t mva)
365{
366#if defined(PROCESSOR_ARCH_armv7_a)
367 DCCMVAU_write(mva);
368#else
369 if (cache_is_unified())
370 CCMVA_write(mva);
371 else
372 DCCMVA_write(mva);
373#endif
374}
375
376/** @}
377 */
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