source: mainline/kernel/arch/arm32/src/atomic.c@ 7328ff4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7328ff4 was 7328ff4, checked in by Jiří Zárevúcky <jiri.zarevucky@…>, 8 years ago

Use builtin memory fences for kernel barriers, and convert smp_coherence() into a regular function

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/*
2 * Copyright (c) 2012 Adam Hraska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief Atomic operations emulation.
34 */
35
36#include <synch/spinlock.h>
37#include <arch/barrier.h>
38
39
40IRQ_SPINLOCK_STATIC_INITIALIZE_NAME(cas_lock, "arm-cas-lock");
41
42/** Implements GCC's missing compare-and-swap intrinsic for ARM.
43 *
44 * Sets \a *ptr to \a new_val if it is equal to \a expected. In any case,
45 * returns the previous value of \a *ptr.
46 */
47void *__sync_val_compare_and_swap_4(void **ptr, void *expected, void *new_val)
48{
49 /*
50 * Using an interrupt disabling spinlock might still lead to deadlock
51 * if CAS() is used in an exception handler. Eg. if a CAS() results
52 * in a page fault exception and the exception handler again tries
53 * to invoke CAS() (even for a different memory location), the spinlock
54 * would deadlock.
55 */
56 irq_spinlock_lock(&cas_lock, true);
57
58 void *cur_val = *ptr;
59
60 if (cur_val == expected) {
61 *ptr = new_val;
62 }
63
64 irq_spinlock_unlock(&cas_lock, true);
65
66 return cur_val;
67}
68
69void __sync_synchronize(void)
70{
71 dsb();
72}
73
74/* Naive implementations of the newer intrinsics. */
75
76_Bool __atomic_compare_exchange_4(void **mem, void **expected, void *desired, _Bool weak, int success, int failure)
77{
78 (void) weak;
79 (void) success;
80 (void) failure;
81
82 void *old = *expected;
83 void *new = __sync_val_compare_and_swap_4(mem, old, desired);
84 if (old == new) {
85 return 1;
86 } else {
87 *expected = new;
88 return 0;
89 }
90}
91
92void *__atomic_exchange_4(void **mem, void *val, int model)
93{
94 (void) model;
95
96 irq_spinlock_lock(&cas_lock, true);
97 void *old = *mem;
98 *mem = val;
99 irq_spinlock_unlock(&cas_lock, true);
100
101 return old;
102}
103
104/** @}
105 */
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