| 1 | /*
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| 2 | * Copyright (c) 2007 Petr Stepan
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup arm32
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| 30 | * @{
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| 31 | */
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| 32 | /**
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| 33 | * @file
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| 34 | * @brief Utilities for convenient manipulation with ARM registers.
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| 35 | */
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| 36 |
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| 37 | #ifndef KERN_arm32_REGUTILS_H_
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| 38 | #define KERN_arm32_REGUTILS_H_
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| 39 |
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| 40 | #define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)
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| 41 | #define STATUS_REG_MODE_MASK 0x1f
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| 42 |
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| 43 | #define CP15_R1_HIGH_VECTORS_BIT (1 << 13)
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| 44 |
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| 45 | /* ARM Processor Operation Modes */
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| 46 | #define USER_MODE 0x10
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| 47 | #define FIQ_MODE 0x11
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| 48 | #define IRQ_MODE 0x12
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| 49 | #define SUPERVISOR_MODE 0x13
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| 50 | #define ABORT_MODE 0x17
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| 51 | #define UNDEFINED_MODE 0x1b
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| 52 | #define SYSTEM_MODE 0x1f
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| 53 |
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| 54 | /* [CS]PRS manipulation macros */
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| 55 | #define GEN_STATUS_READ(nm, reg) \
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| 56 | static inline uint32_t nm## _status_reg_read(void) \
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| 57 | { \
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| 58 | uint32_t retval; \
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| 59 | \
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| 60 | asm volatile ( \
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| 61 | "mrs %[retval], " #reg \
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| 62 | : [retval] "=r" (retval) \
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| 63 | ); \
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| 64 | \
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| 65 | return retval; \
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| 66 | }
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| 67 |
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| 68 | #define GEN_STATUS_WRITE(nm, reg, fieldname, field) \
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| 69 | static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
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| 70 | { \
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| 71 | asm volatile ( \
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| 72 | "msr " #reg "_" #field ", %[value]" \
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| 73 | :: [value] "r" (value) \
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| 74 | ); \
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| 75 | }
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| 76 |
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| 77 | /** Return the value of CPSR (Current Program Status Register). */
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| 78 | GEN_STATUS_READ(current, cpsr);
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| 79 |
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| 80 | /** Set control bits of CPSR. */
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| 81 | GEN_STATUS_WRITE(current, cpsr, control, c);
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| 82 |
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| 83 | /** Return the value of SPSR (Saved Program Status Register). */
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| 84 | GEN_STATUS_READ(saved, spsr);
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| 85 |
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| 86 | #endif
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| 87 |
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| 88 | /** @}
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| 89 | */
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