source: mainline/kernel/arch/arm32/include/cpu.h@ b04ca9c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b04ca9c was bad1f53, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

arm32: Detect caches on armv7

  • Property mode set to 100644
File size: 2.2 KB
Line 
1/*
2 * Copyright (c) 2007 Michal Kebrt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief CPU identification.
34 */
35
36#ifndef KERN_arm32_CPU_H_
37#define KERN_arm32_CPU_H_
38
39#include <typedefs.h>
40#include <arch/asm.h>
41
42enum {
43 ARM_MAX_CACHE_LEVELS = 7,
44};
45
46/** Struct representing ARM CPU identification. */
47typedef struct {
48 /** Implementor (vendor) number. */
49 uint32_t imp_num;
50
51 /** Variant number. */
52 uint32_t variant_num;
53
54 /** Architecture number. */
55 uint32_t arch_num;
56
57 /** Primary part number. */
58 uint32_t prim_part_num;
59
60 /** Revision number. */
61 uint32_t rev_num;
62
63 struct {
64 unsigned ways;
65 unsigned sets;
66 unsigned line_size;
67 unsigned way_shift;
68 unsigned set_shift;
69 } dcache[ARM_MAX_CACHE_LEVELS];
70 unsigned dcache_levels;
71} cpu_arch_t;
72
73#endif
74
75/** @}
76 */
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