| 1 | /*
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| 2 | * Copyright (c) 2005 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup arm32
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Memory barriers.
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| 34 | */
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| 35 |
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| 36 | #ifndef KERN_arm32_BARRIER_H_
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| 37 | #define KERN_arm32_BARRIER_H_
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| 38 |
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| 39 | /*
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| 40 | * TODO: implement true ARM memory barriers for macros below.
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| 41 | * ARMv6 introduced user access of the following commands:
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| 42 | * • Prefetch flush
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| 43 | * • Data synchronization barrier
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| 44 | * • Data memory barrier
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| 45 | * • Clean and prefetch range operations.
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| 46 | * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
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| 47 | */
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| 48 | #define CS_ENTER_BARRIER() asm volatile ("" ::: "memory")
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| 49 | #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory")
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| 50 |
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| 51 | #if defined PROCESSOR_ARCH_armv7_a
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| 52 | /* ARMv7 uses instructions for memory barriers see ARM Architecture reference
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| 53 | * manual for details:
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| 54 | * DMB: ch. A8.8.43 page A8-376
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| 55 | * DSB: ch. A8.8.44 page A8-378
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| 56 | * See ch. A3.8.3 page A3-148 for details about memory barrier implementation
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| 57 | * and functionality on armv7 architecture.
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| 58 | */
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| 59 | #define memory_barrier() asm volatile ("dmb" ::: "memory")
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| 60 | #define read_barrier() asm volatile ("dsb" ::: "memory")
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| 61 | #define write_barrier() asm volatile ("dsb st" ::: "memory")
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| 62 | #elif defined PROCESSOR_ARCH_armv6
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| 63 | /* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
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| 64 | * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
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| 65 | * CP15 implementation is mandatory only for armv6+.
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| 66 | */
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| 67 | #define memory_barrier() asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 5" ::: "r0", "memory")
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| 68 | #define read_barrier() asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 4" ::: "r0", "memory")
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| 69 | #define write_barrier() read_barrier()
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| 70 | #else
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| 71 | /* Older manuals mention syscalls as a way to implement cache coherency and
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| 72 | * barriers. See for example ARM Architecture Reference Manual Version D
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| 73 | * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
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| 74 | */
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| 75 | // TODO implement on per PROCESSOR basis
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| 76 | #define memory_barrier() asm volatile ("" ::: "memory")
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| 77 | #define read_barrier() asm volatile ("" ::: "memory")
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| 78 | #define write_barrier() asm volatile ("" ::: "memory")
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| 79 | #endif
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| 80 |
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| 81 | /*
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| 82 | * There are multiple ways ICache can be implemented on ARM machines. Namely
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| 83 | * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
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| 84 | * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum
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| 85 | * compatibility across processors, ARM recommends that operating systems target
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| 86 | * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
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| 87 | * and do not assume the presence of the IVIPT extension. Software that relies
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| 88 | * on the IVIPT extension might fail in an unpredictable way on an ARMv7
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| 89 | * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
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| 90 | * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
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| 91 | *
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| 92 | * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
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| 93 | * maintenance to other places than just smc.
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| 94 | */
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| 95 |
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| 96 | #ifdef PROCESSOR_ARCH_armv7_a
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| 97 | #define smc_coherence(a) asm volatile ( "isb" ::: "memory")
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| 98 | #define smc_coherence_block(a, l) smc_coherence(a)
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| 99 | #else
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| 100 | /* Available on all supported arms,
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| 101 | * invalidates entire ICache so the written value does not matter. */
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| 102 | //TODO might be PL1 only on armv5 -
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| 103 | #define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
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| 104 | #define smc_coherence_block(a, l) smc_coherence(a)
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| 105 | #endif
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| 106 |
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| 107 |
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| 108 | #endif
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| 109 |
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| 110 | /** @}
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| 111 | */
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