| 1 | /*
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| 2 | * Copyright (c) 2007 Pavel Jancik
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| 3 | * Copyright (c) 2007 Michal Kebrt
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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| 30 | /** @addtogroup arm32mm
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| 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | * @brief Page fault related declarations.
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| 35 | */
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| 36 |
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| 37 | #ifndef KERN_arm32_PAGE_FAULT_H_
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| 38 | #define KERN_arm32_PAGE_FAULT_H_
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| 39 |
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| 40 | #include <stdint.h>
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| 41 |
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| 42 |
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| 43 | /** Decribes CP15 "fault status register" (FSR).
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| 44 | *
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| 45 | * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
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| 46 | * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
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| 47 | * the architecture. A write flag (bit[11] of the DFSR) has also been
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| 48 | * introduced."
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| 49 | * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
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| 50 | *
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| 51 | * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743). for FSR info
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| 52 | */
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| 53 | typedef union {
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| 54 | struct {
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| 55 | unsigned status : 4;
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| 56 | unsigned domain : 4;
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| 57 | unsigned zero : 1;
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| 58 | unsigned lpae : 1; /**< Needs LPAE support implemented */
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| 59 | unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */
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| 60 | unsigned wr : 1; /**< armv6+ only */
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| 61 | unsigned ext : 1 ; /**< external abort */
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| 62 | unsigned cm : 1; /**< Cache maintenance, needs LPAE support */
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| 63 | unsigned should_be_zero : 18;
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| 64 | } data;
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| 65 | struct {
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| 66 | unsigned status : 4;
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| 67 | unsigned sbz0 : 6;
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| 68 | unsigned fs : 1;
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| 69 | unsigned should_be_zero : 21;
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| 70 | } inst;
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| 71 | uint32_t raw;
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| 72 | } fault_status_t;
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| 73 |
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| 74 |
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| 75 | /** Simplified description of instruction code.
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| 76 | *
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| 77 | * @note Used for recognizing memory access instructions.
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| 78 | * @see ARM architecture reference (chapter 3.1)
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| 79 | */
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| 80 | typedef struct {
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| 81 | unsigned dummy1 : 4;
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| 82 | unsigned bit4 : 1;
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| 83 | unsigned bits567 : 3;
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| 84 | unsigned dummy : 12;
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| 85 | unsigned access : 1;
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| 86 | unsigned opcode : 4;
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| 87 | unsigned type : 3;
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| 88 | unsigned condition : 4;
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| 89 | } ATTRIBUTE_PACKED instruction_t;
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| 90 |
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| 91 |
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| 92 | /** Help union used for casting pc register (uint_32_t) value into
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| 93 | * #instruction_t pointer.
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| 94 | */
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| 95 | typedef union {
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| 96 | instruction_t *instr;
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| 97 | uint32_t pc;
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| 98 | } instruction_union_t;
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| 99 |
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| 100 | extern void prefetch_abort(unsigned int, istate_t *);
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| 101 | extern void data_abort(unsigned int, istate_t *);
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| 102 |
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| 103 | #endif
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| 104 |
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| 105 | /** @}
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| 106 | */
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