source: mainline/kernel/arch/arm32/include/arch/cp15.h@ f834cc32

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f834cc32 was f834cc32, checked in by Jakub Jermar <jakub@…>, 10 years ago

More generic detection of TLB type.
  • Property mode set to 100644
File size: 19.0 KB
Line 
1/*
2 * Copyright (c) 2013 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief System Control Coprocessor (CP15)
34 */
35
36#ifndef KERN_arm32_CP15_H_
37#define KERN_arm32_CP15_H_
38
39#if defined(KERNEL) || defined(BOOT)
40#include <typedefs.h>
41#else
42#include <sys/types.h>
43#endif
44
45/** See ARM Architecture reference manual ch. B3.17.1 page B3-1456
46 * for the list */
47
48#define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \
49static inline uint32_t name##_read(void) \
50{ \
51 uint32_t val; \
52 asm volatile ( "mrc p15, "#opc1", %0, "#crn", "#crm", "#opc2"\n" : "=r" (val) ); \
53 return val; \
54}
55#define CONTROL_REG_GEN_WRITE(name, crn, opc1, crm, opc2) \
56static inline void name##_write(uint32_t val) \
57{ \
58 asm volatile ( "mcr p15, "#opc1", %0, "#crn", "#crm", "#opc2"\n" :: "r" (val) ); \
59}
60
61/* Identification registers */
62enum {
63 MIDR_IMPLEMENTER_MASK = 0xff,
64 MIDR_IMPLEMENTER_SHIFT = 24,
65 MIDR_VARIANT_MASK = 0xf,
66 MIDR_VARIANT_SHIFT = 20,
67 MIDR_ARCHITECTURE_MASK = 0xf,
68 MIDR_ARCHITECTURE_SHIFT = 16,
69 MIDR_PART_NUMBER_MASK = 0xfff,
70 MIDR_PART_NUMBER_SHIFT = 4,
71 MIDR_REVISION_MASK = 0xf,
72 MIDR_REVISION_SHIFT = 0,
73};
74CONTROL_REG_GEN_READ(MIDR, c0, 0, c0, 0);
75
76enum {
77 CTR_FORMAT_MASK = 0xe0000000,
78 CTR_FORMAT_ARMv7 = 0x80000000,
79 CTR_FORMAT_ARMv6 = 0x00000000,
80 /* ARMv7 format */
81 CTR_CWG_MASK = 0xf,
82 CTR_CWG_SHIFT = 24,
83 CTR_ERG_MASK = 0xf,
84 CTR_ERG_SHIFT = 20,
85 CTR_D_MIN_LINE_MASK = 0xf,
86 CTR_D_MIN_LINE_SHIFT = 16,
87 CTR_I_MIN_LINE_MASK = 0xf,
88 CTR_I_MIN_LINE_SHIFT = 0,
89 CTR_L1I_POLICY_MASK = 0x0000c000,
90 CTR_L1I_POLICY_AIVIVT = 0x00004000,
91 CTR_L1I_POLICY_VIPT = 0x00008000,
92 CTR_L1I_POLICY_PIPT = 0x0000c000,
93 /* ARMv6 format */
94 CTR_CTYPE_MASK = 0x1e000000,
95 CTR_CTYPE_WT = 0x00000000,
96 CTR_CTYPE_WB_NL = 0x04000000,
97 CTR_CTYPE_WB_D = 0x0a000000,
98 CTR_CTYPE_WB_A = 0x0c000000, /**< ARMv5- only */
99 CTR_CTYPE_WB_B = 0x0e000000, /**< ARMv5- only */
100 CTR_CTYPE_WB_C = 0x1c000000,
101 CTR_SEP_FLAG = 1 << 24,
102 CTR_DCACHE_P_FLAG = 1 << 23,
103 CTR_DCACHE_SIZE_MASK = 0xf,
104 CTR_DCACHE_SIZE_SHIFT = 18,
105 CTR_DCACHE_ASSOC_MASK = 0x7,
106 CTR_DCACHE_ASSOC_SHIFT = 15,
107 CTR_DCACHE_M_FLAG = 1 << 14,
108 CTR_DCACHE_LEN_MASK = 0x3,
109 CTR_DCACHE_LEN_SHIFT = 0,
110 CTR_ICACHE_P_FLAG = 1 << 11,
111 CTR_ICACHE_SIZE_MASK = 0xf,
112 CTR_ICACHE_SIZE_SHIFT = 6,
113 CTR_ICACHE_ASSOC_MASK = 0x7,
114 CTR_ICACHE_ASSOC_SHIFT = 3,
115 CTR_ICACHE_M_FLAG = 1 << 2,
116 CTR_ICACHE_LEN_MASK = 0x3,
117 CTR_ICACHE_LEN_SHIFT = 0,
118};
119CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
120
121#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
122CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2);
123
124enum {
125 TLBTR_SEP_FLAG = 1,
126};
127
128CONTROL_REG_GEN_READ(TLBTR, c0, 0, c0, 3);
129#endif
130
131#if defined(PROCESSOR_ARCH_armv7_a)
132CONTROL_REG_GEN_READ(MPIDR, c0, 0, c0, 5);
133CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6);
134#endif
135
136enum {
137 ID_PFR0_THUMBEE_MASK = 0xf << 12,
138 ID_PFR0_THUMBEE = 0x1 << 12,
139 ID_PFR0_JAZELLE_MASK = 0xf << 8,
140 ID_PFR0_JAZELLE = 0x1 << 8,
141 ID_PFR0_JAZELLE_CV_CLEAR = 0x2 << 8,
142 ID_PFR0_THUMB_MASK = 0xf << 4,
143 ID_PFR0_THUMB = 0x1 << 4,
144 ID_PFR0_THUMB2 = 0x3 << 4,
145 ID_PFR0_ARM_MASK = 0xf << 0,
146 ID_PFR0_ARM = 0x1 << 0,
147};
148CONTROL_REG_GEN_READ(ID_PFR0, c0, 0, c1, 0);
149
150enum {
151 ID_PFR1_GEN_TIMER_EXT_MASK = 0xf << 16,
152 ID_PFR1_GEN_TIMER_EXT = 0x1 << 16,
153 ID_PFR1_VIRT_EXT_MASK = 0xf << 12,
154 ID_PFR1_VIRT_EXT = 0x1 << 12,
155 ID_PFR1_M_PROF_MASK = 0xf << 8,
156 ID_PFR1_M_PROF_MODEL = 0x2 << 8,
157 ID_PFR1_SEC_EXT_MASK = 0xf << 4,
158 ID_PFR1_SEC_EXT = 0x1 << 4,
159 ID_PFR1_SEC_EXT_RFR = 0x2 << 4,
160 ID_PFR1_ARMV4_MODEL_MASK = 0xf << 0,
161 ID_PFR1_ARMV4_MODEL = 0x1 << 0,
162};
163CONTROL_REG_GEN_READ(ID_PFR1, c0, 0, c1, 1);
164CONTROL_REG_GEN_READ(ID_DFR0, c0, 0, c1, 2);
165CONTROL_REG_GEN_READ(ID_AFR0, c0, 0, c1, 3);
166CONTROL_REG_GEN_READ(ID_MMFR0, c0, 0, c1, 4);
167CONTROL_REG_GEN_READ(ID_MMFR1, c0, 0, c1, 5);
168CONTROL_REG_GEN_READ(ID_MMFR2, c0, 0, c1, 6);
169CONTROL_REG_GEN_READ(ID_MMFR3, c0, 0, c1, 7);
170
171CONTROL_REG_GEN_READ(ID_ISAR0, c0, 0, c2, 0);
172CONTROL_REG_GEN_READ(ID_ISAR1, c0, 0, c2, 1);
173CONTROL_REG_GEN_READ(ID_ISAR2, c0, 0, c2, 2);
174CONTROL_REG_GEN_READ(ID_ISAR3, c0, 0, c2, 3);
175CONTROL_REG_GEN_READ(ID_ISAR4, c0, 0, c2, 4);
176CONTROL_REG_GEN_READ(ID_ISAR5, c0, 0, c2, 5);
177
178enum {
179 CCSIDR_WT_FLAG = 1 << 31,
180 CCSIDR_WB_FLAG = 1 << 30,
181 CCSIDR_RA_FLAG = 1 << 29,
182 CCSIDR_WA_FLAG = 1 << 28,
183 CCSIDR_NUMSETS_MASK = 0x7fff,
184 CCSIDR_NUMSETS_SHIFT = 13,
185 CCSIDR_ASSOC_MASK = 0x3ff,
186 CCSIDR_ASSOC_SHIFT = 3,
187 CCSIDR_LINESIZE_MASK = 0x7,
188 CCSIDR_LINESIZE_SHIFT = 0,
189#define CCSIDR_SETS(val) \
190 (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
191#define CCSIDR_WAYS(val) \
192 (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1)
193/* The register value is log(linesize_in_words) - 2 */
194#define CCSIDR_LINESIZE_LOG(val) \
195 (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
196};
197CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
198
199enum {
200 CLIDR_LOUU_MASK = 0x7,
201 CLIDR_LOUU_SHIFT = 27,
202 CLIDR_LOC_MASK = 0x7,
203 CLIDR_LOC_SHIFT = 24,
204 CLIDR_LOUIS_MASK = 0x7,
205 CLIDR_LOUIS_SHIFT = 21,
206 CLIDR_NOCACHE = 0x0,
207 CLIDR_ICACHE_ONLY = 0x1,
208 CLIDR_DCACHE_ONLY = 0x2,
209 CLIDR_SEP_CACHE = 0x3,
210 CLIDR_UNI_CACHE = 0x4,
211 CLIDR_CACHE_MASK = 0x7,
212/** levels counted from 0 */
213#define CLIDR_CACHE(level, val) ((val >> (level * 3)) & CLIDR_CACHE_MASK)
214};
215CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
216CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */
217
218enum {
219 CCSELR_LEVEL_MASK = 0x7,
220 CCSELR_LEVEL_SHIFT = 1,
221 CCSELR_INSTRUCTION_FLAG = 1 << 0,
222};
223CONTROL_REG_GEN_READ(CSSELR, c0, 2, c0, 0);
224CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0);
225CONTROL_REG_GEN_READ(VPIDR, c0, 4, c0, 0);
226CONTROL_REG_GEN_WRITE(VPIDR, c0, 4, c0, 0);
227CONTROL_REG_GEN_READ(VMPIDR, c0, 4, c0, 5);
228CONTROL_REG_GEN_WRITE(VMPIDR, c0, 4, c0, 5);
229
230/* System control registers */
231/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
232 * Manual ARMv7-A and ARMv7-R edition, page 1687 */
233enum {
234 SCTLR_MMU_EN_FLAG = 1 << 0,
235 SCTLR_ALIGN_CHECK_EN_FLAG = 1 << 1, /* Allow alignemnt check */
236 SCTLR_CACHE_EN_FLAG = 1 << 2,
237 SCTLR_CP15_BARRIER_EN_FLAG = 1 << 5,
238 SCTLR_B_EN_FLAG = 1 << 7, /* ARMv6-, big endian switch */
239 SCTLR_SWAP_EN_FLAG = 1 << 10,
240 SCTLR_BRANCH_PREDICT_EN_FLAG = 1 << 11,
241 SCTLR_INST_CACHE_EN_FLAG = 1 << 12,
242 SCTLR_HIGH_VECTORS_EN_FLAG = 1 << 13,
243 SCTLR_ROUND_ROBIN_EN_FLAG = 1 << 14,
244 SCTLR_HW_ACCESS_FLAG_EN_FLAG = 1 << 17,
245 SCTLR_WRITE_XN_EN_FLAG = 1 << 19, /* Only if virt. supported */
246 SCTLR_USPCE_WRITE_XN_EN_FLAG = 1 << 20, /* Only if virt. supported */
247 SCTLR_FAST_IRQ_EN_FLAG = 1 << 21, /* Disable impl. specific feat*/
248 SCTLR_UNALIGNED_EN_FLAG = 1 << 22, /* Must be 1 on armv7 */
249 SCTLR_EXTENDED_PT_EN_FLAG = 1 << 23,
250 SCTLR_IRQ_VECTORS_EN_FLAG = 1 << 24,
251 SCTLR_BIG_ENDIAN_EXC_FLAG = 1 << 25,
252 SCTLR_NMFI_EN_FLAG = 1 << 27,
253 SCTLR_TEX_REMAP_EN_FLAG = 1 << 28,
254 SCTLR_ACCESS_FLAG_EN_FLAG = 1 << 29,
255 SCTLR_THUMB_EXC_EN_FLAG = 1 << 30,
256};
257CONTROL_REG_GEN_READ(SCTLR, c1, 0, c0, 0);
258CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0);
259CONTROL_REG_GEN_READ(ACTLR, c1, 0, c0, 1);
260CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1);
261
262enum {
263 CPACR_ASEDIS_FLAG = 1 << 31,
264 CPACR_D32DIS_FLAG = 1 << 30,
265 CPACR_TRCDIS_FLAG = 1 << 28,
266#define CPACR_CP_MASK(cp) (0x3 << (cp * 2))
267#define CPACR_CP_NO_ACCESS(cp) (0x0 << (cp * 2))
268#define CPACR_CP_PL1_ACCESS(cp) (0x1 << (cp * 2))
269#define CPACR_CP_FULL_ACCESS(cp) (0x3 << (cp * 2))
270};
271CONTROL_REG_GEN_READ(CPACR, c1, 0, c0, 2);
272CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2);
273
274/* Implemented as part of Security extensions */
275enum {
276 SCR_SIF_FLAG = 1 << 9,
277 SCR_HCE_FLAG = 1 << 8,
278 SCR_SCD_FLAG = 1 << 7,
279 SCR_nET_FLAG = 1 << 6,
280 SCR_AW_FLAG = 1 << 5,
281 SCR_FW_FLAG = 1 << 4,
282 SCR_EA_FLAG = 1 << 3,
283 SCR_FIQ_FLAG = 1 << 2,
284 SCR_IRQ_FLAG = 1 << 1,
285 SCR_NS_FLAG = 1 << 0,
286};
287CONTROL_REG_GEN_READ(SCR, c1, 0, c1, 0);
288CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0);
289CONTROL_REG_GEN_READ(SDER, c1, 0, c1, 1);
290CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1);
291
292enum {
293 NSACR_NSTRCDIS_FLAG = 1 << 20,
294 NSACR_RFR_FLAG = 1 << 19,
295 NSACR_NSASEDIS = 1 << 15,
296 NSACR_NSD32DIS = 1 << 14,
297#define NSACR_CP_FLAG(cp) (1 << cp)
298};
299CONTROL_REG_GEN_READ(NSACR, c1, 0, c1, 2);
300CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2);
301
302/* Implemented as part of Virtualization extensions */
303CONTROL_REG_GEN_READ(HSCTLR, c1, 4, c0, 0);
304CONTROL_REG_GEN_WRITE(HSCTLR, c1, 4, c0, 0);
305CONTROL_REG_GEN_READ(HACTLR, c1, 4, c0, 1);
306CONTROL_REG_GEN_WRITE(HACTLR, c1, 4, c0, 1);
307
308CONTROL_REG_GEN_READ(HCR, c1, 4, c1, 0);
309CONTROL_REG_GEN_WRITE(HCR, c1, 4, c1, 0);
310CONTROL_REG_GEN_READ(HDCR, c1, 4, c1, 1);
311CONTROL_REG_GEN_WRITE(HDCR, c1, 4, c1, 1);
312CONTROL_REG_GEN_READ(HCPTR, c1, 4, c1, 2);
313CONTROL_REG_GEN_WRITE(HCPTR, c1, 4, c1, 2);
314CONTROL_REG_GEN_READ(HSTR, c1, 4, c1, 3);
315CONTROL_REG_GEN_WRITE(HSTR, c1, 4, c1, 3);
316CONTROL_REG_GEN_READ(HACR, c1, 4, c1, 7);
317CONTROL_REG_GEN_WRITE(HACR, c1, 4, c1, 7);
318
319/* Memory protection and control registers */
320enum {
321 TTBR_ADDR_MASK = 0xffffff80,
322#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
323 TTBR_NOS_FLAG = 1 << 5,
324 TTBR_RGN_MASK = 0x3 << 3,
325 TTBR_RGN_NO_CACHE = 0x0 << 3,
326 TTBR_RGN_WBWA_CACHE = 0x1 << 3,
327 TTBR_RGN_WT_CACHE = 0x2 << 3,
328 TTBR_RGN_WB_CACHE = 0x3 << 3,
329 TTBR_S_FLAG = 1 << 1,
330 TTBR_C_FLAG = 1 << 0,
331#endif
332};
333CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
334CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
335
336#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
337CONTROL_REG_GEN_READ(TTBR1, c2, 0, c0, 1);
338CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1);
339CONTROL_REG_GEN_READ(TTBCR, c2, 0, c0, 2);
340CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2);
341#endif
342
343#if defined(PROCESSOR_ARCH_armv7)
344CONTROL_REG_GEN_READ(HTCR, c2, 4, c0, 2);
345CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2);
346CONTROL_REG_GEN_READ(VTCR, c2, 4, c1, 2);
347CONTROL_REG_GEN_WRITE(VTCR, c2, 4, c1, 2);
348
349/* PAE */
350CONTROL_REG_GEN_READ(TTBR0H, c2, 0, c2, 0);
351CONTROL_REG_GEN_WRITE(TTBR0H, c2, 0, c2, 0);
352CONTROL_REG_GEN_READ(TTBR1H, c2, 0, c2, 1);
353CONTROL_REG_GEN_WRITE(TTBR1H, c2, 0, c2, 1);
354CONTROL_REG_GEN_READ(HTTBRH, c2, 0, c2, 4);
355CONTROL_REG_GEN_WRITE(HTTBRH, c2, 0, c2, 4);
356CONTROL_REG_GEN_READ(VTTBRH, c2, 0, c2, 6);
357CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6);
358#endif
359
360CONTROL_REG_GEN_READ(DACR, c3, 0, c0, 0);
361CONTROL_REG_GEN_WRITE(DACR, c3, 0, c0, 0);
362
363/* Memory system fault registers */
364CONTROL_REG_GEN_READ(DFSR, c5, 0, c0, 0);
365CONTROL_REG_GEN_WRITE(DFSR, c5, 0, c0, 0);
366CONTROL_REG_GEN_READ(IFSR, c5, 0, c0, 1);
367CONTROL_REG_GEN_WRITE(IFSR, c5, 0, c0, 1);
368
369CONTROL_REG_GEN_READ(ADFSR, c5, 0, c1, 0);
370CONTROL_REG_GEN_WRITE(ADFSR, c5, 0, c1, 0);
371CONTROL_REG_GEN_READ(AIFSR, c5, 0, c1, 1);
372CONTROL_REG_GEN_WRITE(AIFSR, c5, 0, c1, 1);
373
374CONTROL_REG_GEN_READ(HADFSR, c5, 4, c1, 0);
375CONTROL_REG_GEN_WRITE(HADFSR, c5, 4, c1, 0);
376CONTROL_REG_GEN_READ(HAIFSR, c5, 4, c1, 1);
377CONTROL_REG_GEN_WRITE(HAIFSR, c5, 4, c1, 1);
378CONTROL_REG_GEN_READ(HSR, c5, 4, c2, 0);
379CONTROL_REG_GEN_WRITE(HSR, c5, 4, c2, 0);
380
381CONTROL_REG_GEN_READ(DFAR, c6, 0, c0, 0);
382CONTROL_REG_GEN_WRITE(DFAR, c6, 0, c0, 0);
383CONTROL_REG_GEN_READ(IFAR, c6, 0, c0, 2);
384CONTROL_REG_GEN_WRITE(IFAR, c6, 0, c0, 2);
385
386CONTROL_REG_GEN_READ(HDFAR, c6, 4, c0, 0);
387CONTROL_REG_GEN_WRITE(HDFAR, c6, 4, c0, 0);
388CONTROL_REG_GEN_READ(HIFAR, c6, 4, c0, 2);
389CONTROL_REG_GEN_WRITE(HIFAR, c6, 4, c0, 2);
390CONTROL_REG_GEN_READ(HPFAR, c6, 4, c0, 4);
391CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4);
392
393/* Cache maintenance, address translation and other */
394CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4); /* armv6 only */
395CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
396CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
397CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0);
398CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0);
399CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0); /* PAE */
400CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */
401CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
402CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
403CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);
404CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6);
405CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7);
406
407CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
408CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
409
410CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
411CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1);
412CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
413CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
414CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
415CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
416CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
417CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
418
419
420CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
421CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
422CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
423CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
424CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
425
426CONTROL_REG_GEN_WRITE(PFI, c7, 0, c11, 1); /* armv6 only */
427
428CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
429CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
430
431CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0);
432CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1);
433
434/* TLB maintenance */
435#if defined(PROCESSOR_ARCH_armv7_a)
436CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */
437CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */
438CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */
439CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */
440#endif
441
442CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0);
443CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1);
444#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
445CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2);
446#endif
447
448CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0);
449CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1);
450#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
451CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2);
452#endif
453
454CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
455CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
456#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
457CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);
458#endif
459#if defined(PROCESSOR_ARCH_armv7_a)
460CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3);
461#endif
462
463#if defined(PROCESSOR_ARCH_armv7_a)
464CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */
465CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */
466CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */
467#endif
468
469#if defined(PROCESSOR_ARCH_armv7_a)
470CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0);
471CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1);
472CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
473#endif
474
475/* c9 are performance monitoring resgisters */
476enum {
477 PMCR_IMP_MASK = 0xff,
478 PMCR_IMP_SHIFT = 24,
479 PMCR_IDCODE_MASK = 0xff,
480 PMCR_IDCODE_SHIFT = 16,
481 PMCR_EVENT_NUM_MASK = 0x1f,
482 PMCR_EVENT_NUM_SHIFT = 11,
483 PMCR_DP_FLAG = 1 << 5,
484 PMCR_X_FLAG = 1 << 4,
485 PMCR_D_FLAG = 1 << 3,
486 PMCR_C_FLAG = 1 << 2,
487 PMCR_P_FLAG = 1 << 1,
488 PMCR_E_FLAG = 1 << 0,
489};
490CONTROL_REG_GEN_READ(PMCR, c9, 0, c12, 0);
491CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0);
492enum {
493 PMCNTENSET_CYCLE_COUNTER_EN_FLAG = 1 << 31,
494#define PMCNTENSET_COUNTER_EN_FLAG(c) (1 << c)
495};
496CONTROL_REG_GEN_READ(PMCNTENSET, c9, 0, c12, 1);
497CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1);
498CONTROL_REG_GEN_READ(PMCCNTR, c9, 0, c13, 0);
499CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0);
500
501
502/*c10 has tons of reserved too */
503CONTROL_REG_GEN_READ(PRRR, c10, 0, c2, 0); /* no PAE */
504CONTROL_REG_GEN_WRITE(PRRR, c10, 0, c2, 0); /* no PAE */
505CONTROL_REG_GEN_READ(MAIR0, c10, 0, c2, 0); /* PAE */
506CONTROL_REG_GEN_WRITE(MAIR0, c10, 0, c2, 0); /* PAE */
507CONTROL_REG_GEN_READ(NMRR, c10, 0, c2, 1); /* no PAE */
508CONTROL_REG_GEN_WRITE(NMRR, c10, 0, c2, 1); /* no PAE */
509CONTROL_REG_GEN_READ(MAIR1, c10, 0, c2, 1); /* PAE */
510CONTROL_REG_GEN_WRITE(MAIR1, c10, 0, c2, 1); /* PAE */
511
512CONTROL_REG_GEN_READ(AMAIR0, c10, 0, c3, 0); /* PAE */
513CONTROL_REG_GEN_WRITE(AMAIR0, c10, 0, c3, 0); /* PAE */
514CONTROL_REG_GEN_READ(AMAIR1, c10, 0, c3, 1); /* PAE */
515CONTROL_REG_GEN_WRITE(AMAIR1, c10, 0, c3, 1); /* PAE */
516
517CONTROL_REG_GEN_READ(HMAIR0, c10, 4, c2, 0);
518CONTROL_REG_GEN_WRITE(HMAIR0, c10, 4, c2, 0);
519CONTROL_REG_GEN_READ(HMAIR1, c10, 4, c2, 1);
520CONTROL_REG_GEN_WRITE(HMAIR1, c10, 4, c2, 1);
521
522CONTROL_REG_GEN_READ(HAMAIR0, c10, 4, c3, 0);
523CONTROL_REG_GEN_WRITE(HAMAIR0, c10, 4, c3, 0);
524CONTROL_REG_GEN_READ(HAMAIR1, c10, 4, c3, 1);
525CONTROL_REG_GEN_WRITE(HAMAIR1, c10, 4, c3, 1);
526
527/* c11 is reserved for TCM and DMA */
528
529/* Security extensions */
530CONTROL_REG_GEN_READ(VBAR, c12, 0, c0, 0);
531CONTROL_REG_GEN_WRITE(VBAR, c12, 0, c0, 0);
532CONTROL_REG_GEN_READ(MVBAR, c12, 0, c0, 1);
533CONTROL_REG_GEN_WRITE(MVBAR, c12, 0, c0, 1);
534
535CONTROL_REG_GEN_READ(ISR, c12, 0, c1, 0);
536
537CONTROL_REG_GEN_READ(HVBAR, c12, 4, c0, 0);
538CONTROL_REG_GEN_WRITE(HVBAR, c12, 4, c0, 0);
539
540/* Process context and thread id (FCSE) */
541CONTROL_REG_GEN_READ(FCSEIDR, c13, 0, c0, 0);
542
543CONTROL_REG_GEN_READ(CONTEXTIDR, c13, 0, c0, 1);
544CONTROL_REG_GEN_WRITE(CONTEXTIDR, c13, 0, c0, 1);
545CONTROL_REG_GEN_READ(TPIDRURW, c13, 0, c0, 2);
546CONTROL_REG_GEN_WRITE(TPIDRURW, c13, 0, c0, 2);
547CONTROL_REG_GEN_READ(TPIDRURO, c13, 0, c0, 3);
548CONTROL_REG_GEN_WRITE(TPIDRURO, c13, 0, c0, 3);
549CONTROL_REG_GEN_READ(TPIDRPRW, c13, 0, c0, 4);
550CONTROL_REG_GEN_WRITE(TPIDRPRW, c13, 0, c0, 4);
551
552CONTROL_REG_GEN_READ(HTPIDR, c13, 4, c0, 2);
553CONTROL_REG_GEN_WRITE(HTPIDR, c13, 4, c0, 2);
554
555/* Generic Timer Extensions */
556CONTROL_REG_GEN_READ(CNTFRQ, c14, 0, c0, 0);
557CONTROL_REG_GEN_WRITE(CNTFRQ, c14, 0, c0, 0);
558CONTROL_REG_GEN_READ(CNTKCTL, c14, 0, c1, 0);
559CONTROL_REG_GEN_WRITE(CNTKCTL, c14, 0, c1, 0);
560
561CONTROL_REG_GEN_READ(CNTP_TVAL, c14, 0, c2, 0);
562CONTROL_REG_GEN_WRITE(CNTP_TVAL, c14, 0, c2, 0);
563CONTROL_REG_GEN_READ(CNTP_CTL, c14, 0, c2, 1);
564CONTROL_REG_GEN_WRITE(CNTP_CTL, c14, 0, c2, 1);
565
566CONTROL_REG_GEN_READ(CNTV_TVAL, c14, 0, c3, 0);
567CONTROL_REG_GEN_WRITE(CNTV_TVAL, c14, 0, c3, 0);
568CONTROL_REG_GEN_READ(CNTV_CTL, c14, 0, c3, 1);
569CONTROL_REG_GEN_WRITE(CNTV_CTL, c14, 0, c3, 1);
570
571CONTROL_REG_GEN_READ(CNTHCTL, c14, 4, c1, 0);
572CONTROL_REG_GEN_WRITE(CNTHCTL, c14, 4, c1, 0);
573
574CONTROL_REG_GEN_READ(CNTHP_TVAL, c14, 4, c2, 0);
575CONTROL_REG_GEN_WRITE(CNTHP_TVAL, c14, 4, c2, 0);
576CONTROL_REG_GEN_READ(CNTHP_CTL, c14, 4, c2, 1);
577CONTROL_REG_GEN_WRITE(CNTHP_CTL, c14, 4, c2, 1);
578
579#endif
580
581/** @}
582 */
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