source: mainline/kernel/arch/arm32/include/arch/cache.h@ 93d8022

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 93d8022 was 93d8022, checked in by Jakub Jermar <jakub@…>, 10 years ago

ARM cache handling fixes

  • boot: Use the normal outer and inner WBWA attribute also for ARMv6
  • kernel: Fix comment in page_armv6.h:set_pt_level0_flags(). TEX=5, C=0, B=1 encodes outer and inner WBWA normal memory.
  • Treat all normal memory as non shareable also on ARMv6.
  • Make sure D$ is invalidated in cpu_arch_init() before it is enabled.
  • For non-cacheable ARMv6+ memory, use device memory type instead of strongly-ordered.
  • For ARMv5-, use either cached/buffered (CB=0b11) or uncached/unbuffered (CB=0b00).
  • Property mode set to 100644
File size: 1.9 KB
RevLine 
[bad1f53]1/*
2 * Copyright (c) 2013 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32
30 * @{
31 */
32/** @file
33 * @brief Security Extensions Routines
34 */
35
36#ifndef KERN_arm32_CACHE_H_
37#define KERN_arm32_CACHE_H_
38
[d5610b9]39#include <typedefs.h>
40
[bad1f53]41unsigned dcache_levels(void);
42
43void dcache_flush(void);
44void dcache_flush_invalidate(void);
45void cpu_dcache_flush(void);
46void cpu_dcache_flush_invalidate(void);
[d5610b9]47extern void icache_invalidate(void);
[93d8022]48extern void dcache_invalidate(void);
[d5610b9]49extern void dcache_clean_mva_pou(uintptr_t);
[bad1f53]50
51#endif
52/** @}
53 */
54
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