source: mainline/kernel/arch/amd64/src/syscall.c@ e13daa5d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e13daa5d was e13daa5d, checked in by Jakub Jermar <jakub@…>, 17 years ago

Fortify ia32 and amd64 kernels against mallicious uspace applications that set
DF prior to entering the kernel. For AMD64 syscalls, we don't use the CLD
instruction, but make use of the SFMASK MSR instead. Simics works fine with
it, but QEMU seems to have a problem.

  • Property mode set to 100644
File size: 2.5 KB
Line 
1/*
2 * Copyright (c) 2006 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 */
34
35#include <syscall/syscall.h>
36#include <arch/syscall.h>
37#include <panic.h>
38#include <arch/cpu.h>
39#include <arch/pm.h>
40#include <arch/asm.h>
41
42#include <print.h>
43#include <arch/cpu.h>
44
45extern void syscall_entry(void);
46
47/** Enable & setup support for SYSCALL/SYSRET */
48void syscall_setup_cpu(void)
49{
50 /* Enable SYSCALL/SYSRET */
51 set_efer_flag(AMD_SCE_FLAG);
52
53 /* Setup syscall entry address */
54
55 /* This is _mess_ - the 64-bit CS is argument + 16,
56 * the SS is argument + 8. The order is:
57 * +0(KDATA_DES), +8(UDATA_DES), +16(UTEXT_DES)
58 */
59 write_msr(AMD_MSR_STAR,
60 ((uint64_t)(gdtselector(KDATA_DES) | PL_USER) << 48) |
61 ((uint64_t)(gdtselector(KTEXT_DES) | PL_KERNEL) << 32));
62 write_msr(AMD_MSR_LSTAR, (uint64_t)syscall_entry);
63 /* Mask RFLAGS on syscall
64 * - disable interrupts, until we exchange the stack register
65 * (mask the IF bit)
66 * - clear DF so that the string instructions operate in
67 * the right direction
68 */
69 write_msr(AMD_MSR_SFMASK, RFLAGS_IF | RFLAGS_DF);
70}
71
72/** @}
73 */
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