source: mainline/kernel/arch/amd64/src/interrupt.c@ fd67c9f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since fd67c9f was fd67c9f, checked in by Jakub Jermar <jakub@…>, 6 years ago

Handle PIC spurious IRQs with care
  • Property mode set to 100644
File size: 7.0 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_amd64_interrupt
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/interrupt.h>
36#include <assert.h>
37#include <log.h>
38#include <panic.h>
39#include <genarch/drivers/i8259/i8259.h>
40#include <halt.h>
41#include <cpu.h>
42#include <arch/asm.h>
43#include <mm/tlb.h>
44#include <mm/as.h>
45#include <arch.h>
46#include <proc/scheduler.h>
47#include <proc/thread.h>
48#include <proc/task.h>
49#include <synch/spinlock.h>
50#include <arch/ddi/ddi.h>
51#include <interrupt.h>
52#include <ddi/irq.h>
53#include <symtab.h>
54#include <stacktrace.h>
55
56/*
57 * Interrupt and exception dispatching.
58 */
59
60void (*disable_irqs_function)(uint16_t irqmask) = NULL;
61void (*enable_irqs_function)(uint16_t irqmask) = NULL;
62void (*eoi_function)(unsigned int) = NULL;
63const char *irqs_info = NULL;
64
65void istate_decode(istate_t *istate)
66{
67 log_printf("cs =%0#18" PRIx64 "\trip=%0#18" PRIx64 "\t"
68 "rfl=%0#18" PRIx64 "\terr=%0#18" PRIx64 "\n",
69 istate->cs, istate->rip, istate->rflags, istate->error_word);
70
71 if (istate_from_uspace(istate))
72 log_printf("ss =%0#18" PRIx64 "\n", istate->ss);
73
74 log_printf("rax=%0#18" PRIx64 "\trbx=%0#18" PRIx64 "\t"
75 "rcx=%0#18" PRIx64 "\trdx=%0#18" PRIx64 "\n",
76 istate->rax, istate->rbx, istate->rcx, istate->rdx);
77
78 log_printf("rsi=%0#18" PRIx64 "\trdi=%0#18" PRIx64 "\t"
79 "rbp=%0#18" PRIx64 "\trsp=%0#18" PRIx64 "\n",
80 istate->rsi, istate->rdi, istate->rbp,
81 istate_from_uspace(istate) ? istate->rsp :
82 (uintptr_t) &istate->rsp);
83
84 log_printf("r8 =%0#18" PRIx64 "\tr9 =%0#18" PRIx64 "\t"
85 "r10=%0#18" PRIx64 "\tr11=%0#18" PRIx64 "\n",
86 istate->r8, istate->r9, istate->r10, istate->r11);
87
88 log_printf("r12=%0#18" PRIx64 "\tr13=%0#18" PRIx64 "\t"
89 "r14=%0#18" PRIx64 "\tr15=%0#18" PRIx64 "\n",
90 istate->r12, istate->r13, istate->r14, istate->r15);
91}
92
93static void trap_virtual_eoi(unsigned int irq)
94{
95 if (eoi_function)
96 eoi_function(irq);
97 else
98 panic("No eoi_function.");
99
100}
101
102static void null_interrupt(unsigned int n, istate_t *istate)
103{
104 fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
105 panic_badtrap(istate, n, "Unserviced interrupt.");
106}
107
108static void de_fault(unsigned int n, istate_t *istate)
109{
110 fault_if_from_uspace(istate, "Divide error.");
111 panic_badtrap(istate, n, "Divide error.");
112}
113
114/** General Protection Fault.
115 *
116 */
117static void gp_fault(unsigned int n, istate_t *istate)
118{
119 if (TASK) {
120 irq_spinlock_lock(&TASK->lock, false);
121 size_t ver = TASK->arch.iomapver;
122 irq_spinlock_unlock(&TASK->lock, false);
123
124 if (CPU->arch.iomapver_copy != ver) {
125 /*
126 * This fault can be caused by an early access
127 * to I/O port because of an out-dated
128 * I/O Permission bitmap installed on CPU.
129 * Install the fresh copy and restart
130 * the instruction.
131 */
132 io_perm_bitmap_install();
133 return;
134 }
135 fault_if_from_uspace(istate, "General protection fault.");
136 }
137 panic_badtrap(istate, n, "General protection fault.");
138}
139
140static void ss_fault(unsigned int n, istate_t *istate)
141{
142 fault_if_from_uspace(istate, "Stack fault.");
143 panic_badtrap(istate, n, "Stack fault.");
144}
145
146static void nm_fault(unsigned int n, istate_t *istate)
147{
148#ifdef CONFIG_FPU_LAZY
149 scheduler_fpu_lazy_request();
150#else
151 fault_if_from_uspace(istate, "FPU fault.");
152 panic("FPU fault.");
153#endif
154}
155
156#ifdef CONFIG_SMP
157static void tlb_shootdown_ipi(unsigned int n, istate_t *istate)
158{
159 trap_virtual_eoi(0);
160 tlb_shootdown_ipi_recv();
161}
162#endif
163
164/** Handler of IRQ exceptions.
165 *
166 */
167static void irq_interrupt(unsigned int n, istate_t *istate)
168{
169 assert(n >= IVT_IRQBASE);
170
171 unsigned int inum = n - IVT_IRQBASE;
172 bool ack = false;
173 assert(inum < IRQ_COUNT);
174 assert(inum != IRQ_PIC1);
175
176 irq_t *irq = irq_dispatch_and_lock(inum);
177 if (irq) {
178 /*
179 * The IRQ handler was found.
180 */
181
182 if (irq->preack) {
183 /* Send EOI before processing the interrupt */
184 trap_virtual_eoi(inum);
185 ack = true;
186 }
187 irq->handler(irq);
188 irq_spinlock_unlock(&irq->lock, false);
189 } else {
190#ifdef CONFIG_DEBUG
191 log(LF_ARCH, LVL_DEBUG, "cpu%u: unhandled IRQ %u", CPU->id,
192 inum);
193#endif
194 }
195
196 if (!ack)
197 trap_virtual_eoi(inum);
198}
199
200static void pic_spurious(unsigned int n, istate_t *istate)
201{
202 unsigned int inum = n - IVT_IRQBASE;
203 if (!pic_is_spurious(inum)) {
204 /* This is actually not a spurious IRQ, so proceed as usual. */
205 irq_interrupt(n, istate);
206 return;
207 }
208 pic_handle_spurious(n);
209#ifdef CONFIG_DEBUG
210 log(LF_ARCH, LVL_DEBUG, "cpu%u: PIC spurious interrupt %u", CPU->id,
211 inum);
212#endif
213}
214
215void interrupt_init(void)
216{
217 unsigned int i;
218
219 for (i = 0; i < IVT_ITEMS; i++)
220 exc_register(i, "null", false, (iroutine_t) null_interrupt);
221
222 for (i = 0; i < IRQ_COUNT; i++) {
223 if ((i != IRQ_PIC0_SPUR) && (i != IRQ_PIC1_SPUR) &&
224 (i != IRQ_PIC1))
225 exc_register(IVT_IRQBASE + i, "irq", true,
226 (iroutine_t) irq_interrupt);
227 }
228
229 exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault);
230 exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault);
231 exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault);
232 exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault);
233 exc_register(VECTOR_PIC0_SPUR, "pic0_spurious", true,
234 (iroutine_t) pic_spurious);
235 exc_register(VECTOR_PIC1_SPUR, "pic1_spurious", true,
236 (iroutine_t) pic_spurious);
237
238#ifdef CONFIG_SMP
239 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
240 (iroutine_t) tlb_shootdown_ipi);
241#endif
242}
243
244void trap_virtual_enable_irqs(uint16_t irqmask)
245{
246 if (enable_irqs_function)
247 enable_irqs_function(irqmask);
248 else
249 panic("No enable_irqs_function.");
250}
251
252void trap_virtual_disable_irqs(uint16_t irqmask)
253{
254 if (disable_irqs_function)
255 disable_irqs_function(irqmask);
256 else
257 panic("No disable_irqs_function.");
258}
259
260/** @}
261 */
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