[db3341e] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[db3341e] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[c5429fe] | 29 | /** @addtogroup kernel_amd64_interrupt
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[db3341e] | 35 | #include <arch/interrupt.h>
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[63e27ef] | 36 | #include <assert.h>
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[b2fa1204] | 37 | #include <log.h>
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[db3341e] | 38 | #include <panic.h>
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[80d31883] | 39 | #include <arch/drivers/i8259.h>
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[b2e121a] | 40 | #include <halt.h>
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[db3341e] | 41 | #include <cpu.h>
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| 42 | #include <arch/asm.h>
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| 43 | #include <mm/tlb.h>
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[20d50a1] | 44 | #include <mm/as.h>
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[db3341e] | 45 | #include <arch.h>
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[b49f4ae] | 46 | #include <proc/scheduler.h>
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[1084a784] | 47 | #include <proc/thread.h>
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[2382d09] | 48 | #include <proc/task.h>
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| 49 | #include <synch/spinlock.h>
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| 50 | #include <arch/ddi/ddi.h>
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[5626277] | 51 | #include <interrupt.h>
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[8607db8] | 52 | #include <ddi/irq.h>
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[e2b762ec] | 53 | #include <symtab.h>
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[304342e] | 54 | #include <stacktrace.h>
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[e2b762ec] | 55 |
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[8607db8] | 56 | /*
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| 57 | * Interrupt and exception dispatching.
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| 58 | */
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| 59 |
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[1433ecda] | 60 | void (*disable_irqs_function)(uint16_t irqmask) = NULL;
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| 61 | void (*enable_irqs_function)(uint16_t irqmask) = NULL;
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| 62 | void (*eoi_function)(void) = NULL;
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[acc7ce4] | 63 | const char *irqs_info = NULL;
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[8607db8] | 64 |
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[22a28a69] | 65 | void istate_decode(istate_t *istate)
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[8ec9bae] | 66 | {
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[b2fa1204] | 67 | log_printf("cs =%0#18" PRIx64 "\trip=%0#18" PRIx64 "\t"
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[2438fa6] | 68 | "rfl=%0#18" PRIx64 "\terr=%0#18" PRIx64 "\n",
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| 69 | istate->cs, istate->rip, istate->rflags, istate->error_word);
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[a35b458] | 70 |
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[9171f12] | 71 | if (istate_from_uspace(istate))
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[b2fa1204] | 72 | log_printf("ss =%0#18" PRIx64 "\n", istate->ss);
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[a35b458] | 73 |
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[b2fa1204] | 74 | log_printf("rax=%0#18" PRIx64 "\trbx=%0#18" PRIx64 "\t"
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[2438fa6] | 75 | "rcx=%0#18" PRIx64 "\trdx=%0#18" PRIx64 "\n",
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[9171f12] | 76 | istate->rax, istate->rbx, istate->rcx, istate->rdx);
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[a35b458] | 77 |
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[b2fa1204] | 78 | log_printf("rsi=%0#18" PRIx64 "\trdi=%0#18" PRIx64 "\t"
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[2438fa6] | 79 | "rbp=%0#18" PRIx64 "\trsp=%0#18" PRIx64 "\n",
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| 80 | istate->rsi, istate->rdi, istate->rbp,
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| 81 | istate_from_uspace(istate) ? istate->rsp :
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| 82 | (uintptr_t) &istate->rsp);
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[a35b458] | 83 |
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[b2fa1204] | 84 | log_printf("r8 =%0#18" PRIx64 "\tr9 =%0#18" PRIx64 "\t"
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[2438fa6] | 85 | "r10=%0#18" PRIx64 "\tr11=%0#18" PRIx64 "\n",
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[9171f12] | 86 | istate->r8, istate->r9, istate->r10, istate->r11);
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[a35b458] | 87 |
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[b2fa1204] | 88 | log_printf("r12=%0#18" PRIx64 "\tr13=%0#18" PRIx64 "\t"
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[2438fa6] | 89 | "r14=%0#18" PRIx64 "\tr15=%0#18" PRIx64 "\n",
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[9171f12] | 90 | istate->r12, istate->r13, istate->r14, istate->r15);
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[8ec9bae] | 91 | }
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[db3341e] | 92 |
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[8607db8] | 93 | static void trap_virtual_eoi(void)
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| 94 | {
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| 95 | if (eoi_function)
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| 96 | eoi_function();
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| 97 | else
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[f651e80] | 98 | panic("No eoi_function.");
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[db3341e] | 99 |
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[8607db8] | 100 | }
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[db3341e] | 101 |
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[214ec25c] | 102 | static void null_interrupt(unsigned int n, istate_t *istate)
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[db3341e] | 103 | {
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[214ec25c] | 104 | fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
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[a043e39] | 105 | panic_badtrap(istate, n, "Unserviced interrupt.");
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[db3341e] | 106 | }
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| 107 |
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[214ec25c] | 108 | static void de_fault(unsigned int n, istate_t *istate)
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[4491338] | 109 | {
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| 110 | fault_if_from_uspace(istate, "Divide error.");
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[a043e39] | 111 | panic_badtrap(istate, n, "Divide error.");
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[4491338] | 112 | }
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| 113 |
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[da1bafb] | 114 | /** General Protection Fault.
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| 115 | *
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| 116 | */
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[214ec25c] | 117 | static void gp_fault(unsigned int n, istate_t *istate)
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[db3341e] | 118 | {
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[2382d09] | 119 | if (TASK) {
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[da1bafb] | 120 | irq_spinlock_lock(&TASK->lock, false);
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| 121 | size_t ver = TASK->arch.iomapver;
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| 122 | irq_spinlock_unlock(&TASK->lock, false);
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[a35b458] | 123 |
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[2382d09] | 124 | if (CPU->arch.iomapver_copy != ver) {
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| 125 | /*
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| 126 | * This fault can be caused by an early access
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| 127 | * to I/O port because of an out-dated
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| 128 | * I/O Permission bitmap installed on CPU.
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| 129 | * Install the fresh copy and restart
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| 130 | * the instruction.
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| 131 | */
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| 132 | io_perm_bitmap_install();
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| 133 | return;
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| 134 | }
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[f651e80] | 135 | fault_if_from_uspace(istate, "General protection fault.");
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[2382d09] | 136 | }
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[a043e39] | 137 | panic_badtrap(istate, n, "General protection fault.");
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[db3341e] | 138 | }
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| 139 |
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[214ec25c] | 140 | static void ss_fault(unsigned int n, istate_t *istate)
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[db3341e] | 141 | {
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[f651e80] | 142 | fault_if_from_uspace(istate, "Stack fault.");
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[a043e39] | 143 | panic_badtrap(istate, n, "Stack fault.");
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[db3341e] | 144 | }
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| 145 |
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[214ec25c] | 146 | static void nm_fault(unsigned int n, istate_t *istate)
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[db3341e] | 147 | {
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[6da1013f] | 148 | #ifdef CONFIG_FPU_LAZY
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[b49f4ae] | 149 | scheduler_fpu_lazy_request();
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| 150 | #else
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[f651e80] | 151 | fault_if_from_uspace(istate, "FPU fault.");
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| 152 | panic("FPU fault.");
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[b49f4ae] | 153 | #endif
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[db3341e] | 154 | }
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| 155 |
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[cbc8ac6] | 156 | #ifdef CONFIG_SMP
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[214ec25c] | 157 | static void tlb_shootdown_ipi(unsigned int n, istate_t *istate)
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[db3341e] | 158 | {
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| 159 | trap_virtual_eoi();
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| 160 | tlb_shootdown_ipi_recv();
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| 161 | }
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[cbc8ac6] | 162 | #endif
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[db3341e] | 163 |
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[da1bafb] | 164 | /** Handler of IRQ exceptions.
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| 165 | *
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| 166 | */
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[214ec25c] | 167 | static void irq_interrupt(unsigned int n, istate_t *istate)
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[8607db8] | 168 | {
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[63e27ef] | 169 | assert(n >= IVT_IRQBASE);
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[a35b458] | 170 |
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[214ec25c] | 171 | unsigned int inum = n - IVT_IRQBASE;
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[7bcfbbc] | 172 | bool ack = false;
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[63e27ef] | 173 | assert(inum < IRQ_COUNT);
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| 174 | assert((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1));
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[a35b458] | 175 |
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[8607db8] | 176 | irq_t *irq = irq_dispatch_and_lock(inum);
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| 177 | if (irq) {
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| 178 | /*
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| 179 | * The IRQ handler was found.
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| 180 | */
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[a35b458] | 181 |
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[7bcfbbc] | 182 | if (irq->preack) {
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| 183 | /* Send EOI before processing the interrupt */
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| 184 | trap_virtual_eoi();
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| 185 | ack = true;
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| 186 | }
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[6cd9aa6] | 187 | irq->handler(irq);
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[da1bafb] | 188 | irq_spinlock_unlock(&irq->lock, false);
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[8607db8] | 189 | } else {
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| 190 | /*
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| 191 | * Spurious interrupt.
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| 192 | */
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| 193 | #ifdef CONFIG_DEBUG
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[b2fa1204] | 194 | log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious interrupt (inum=%u)",
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| 195 | CPU->id, inum);
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[8607db8] | 196 | #endif
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| 197 | }
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[a35b458] | 198 |
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[7bcfbbc] | 199 | if (!ack)
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| 200 | trap_virtual_eoi();
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[8607db8] | 201 | }
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| 202 |
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| 203 | void interrupt_init(void)
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| 204 | {
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[b3b7e14a] | 205 | unsigned int i;
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[a35b458] | 206 |
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[8607db8] | 207 | for (i = 0; i < IVT_ITEMS; i++)
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[b3b7e14a] | 208 | exc_register(i, "null", false, (iroutine_t) null_interrupt);
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[a35b458] | 209 |
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[8607db8] | 210 | for (i = 0; i < IRQ_COUNT; i++) {
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| 211 | if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1))
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[b3b7e14a] | 212 | exc_register(IVT_IRQBASE + i, "irq", true,
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| 213 | (iroutine_t) irq_interrupt);
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[8607db8] | 214 | }
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[a35b458] | 215 |
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[4b0206c] | 216 | exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault);
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| 217 | exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault);
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| 218 | exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault);
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| 219 | exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault);
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[a35b458] | 220 |
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[8607db8] | 221 | #ifdef CONFIG_SMP
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[b3b7e14a] | 222 | exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
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| 223 | (iroutine_t) tlb_shootdown_ipi);
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[8607db8] | 224 | #endif
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| 225 | }
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| 226 |
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[7f1c620] | 227 | void trap_virtual_enable_irqs(uint16_t irqmask)
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[db3341e] | 228 | {
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| 229 | if (enable_irqs_function)
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| 230 | enable_irqs_function(irqmask);
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| 231 | else
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[f651e80] | 232 | panic("No enable_irqs_function.");
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[db3341e] | 233 | }
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| 234 |
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[7f1c620] | 235 | void trap_virtual_disable_irqs(uint16_t irqmask)
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[db3341e] | 236 | {
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| 237 | if (disable_irqs_function)
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| 238 | disable_irqs_function(irqmask);
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| 239 | else
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[f651e80] | 240 | panic("No disable_irqs_function.");
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[db3341e] | 241 | }
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| 242 |
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[06e1e95] | 243 | /** @}
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[b45c443] | 244 | */
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