source: mainline/kernel/arch/amd64/src/fpu_context.c@ d8bb821

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d8bb821 was 24c394b, checked in by Jakub Jermar <jakub@…>, 11 years ago

Use directly the fpu member of the fpu_context_t in the "m" constraint.

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Vana
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 *
34 */
35
36#include <fpu_context.h>
37
38/** Save FPU (mmx, sse) context using fxsave instruction */
39void fpu_context_save(fpu_context_t *fctx)
40{
41 asm volatile (
42 "fxsave %[fctx]\n"
43 : [fctx] "=m" (fctx->fpu)
44 );
45}
46
47/** Restore FPU (mmx,sse) context using fxrstor instruction */
48void fpu_context_restore(fpu_context_t *fctx)
49{
50 asm volatile (
51 "fxrstor %[fctx]\n"
52 : [fctx] "=m" (fctx->fpu)
53 );
54}
55
56void fpu_init()
57{
58 /* TODO: Zero all SSE, MMX etc. registers */
59 /* Default value of SCR register is 0x1f80,
60 * it masks all FPU exceptions*/
61 asm volatile (
62 "fninit\n"
63 );
64}
65
66/** @}
67 */
Note: See TracBrowser for help on using the repository browser.