source: mainline/kernel/arch/amd64/src/fpu_context.c@ ddf1255

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ddf1255 was b3f8fb7, checked in by Martin Decky <martin@…>, 19 years ago

huge type system cleanup
remove cyclical type dependencies across multiple header files
many minor coding style fixes

  • Property mode set to 100644
File size: 1.9 KB
RevLine 
[1141c1a]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Vana
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
[b45c443]27 */
28
[27ab6a7]29/** @addtogroup amd64
[b45c443]30 * @{
31 */
32/** @file
[3396f59]33 *
[1141c1a]34 */
35
[3396f59]36#include <fpu_context.h>
37
[3156582]38/** Save FPU (mmx, sse) context using fxsave instruction */
[3396f59]39void fpu_context_save(fpu_context_t *fctx)
40{
[e7b7be3f]41 asm volatile (
[3396f59]42 "fxsave %0"
43 : "=m"(*fctx)
44 );
45}
[1141c1a]46
[3156582]47/** Restore FPU (mmx,sse) context using fxrstor instruction */
[b49f4ae]48void fpu_context_restore(fpu_context_t *fctx)
[3396f59]49{
[e7b7be3f]50 asm volatile (
[3396f59]51 "fxrstor %0"
52 : "=m"(*fctx)
53 );
54}
[1141c1a]55
[f76fed4]56void fpu_init()
[3396f59]57{
[ffc277e]58 /* TODO: Zero all SSE, MMX etc. registers */
[e7b7be3f]59 asm volatile (
[3396f59]60 "fninit;"
61 );
62}
[b45c443]63
[27ab6a7]64/** @}
[b45c443]65 */
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