source: mainline/kernel/arch/amd64/src/fpu_context.c@ 11675207

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 11675207 was 11675207, checked in by jermar <jermar@…>, 17 years ago

Move everything to kernel/.

  • Property mode set to 100644
File size: 2.0 KB
RevLine 
[1141c1a]1/*
[3396f59]2 * Copyright (C) 2005 Jakub Vana
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
[b45c443]27 */
28
29 /** @addtogroup amd64
30 * @{
31 */
32/** @file
[3396f59]33 *
[1141c1a]34 */
35
[3396f59]36#include <fpu_context.h>
37#include <arch.h>
38#include <cpu.h>
39
[3156582]40/** Save FPU (mmx, sse) context using fxsave instruction */
[3396f59]41void fpu_context_save(fpu_context_t *fctx)
42{
43 __asm__ volatile (
44 "fxsave %0"
45 : "=m"(*fctx)
46 );
47}
[1141c1a]48
[3156582]49/** Restore FPU (mmx,sse) context using fxrstor instruction */
[b49f4ae]50void fpu_context_restore(fpu_context_t *fctx)
[3396f59]51{
52 __asm__ volatile (
53 "fxrstor %0"
54 : "=m"(*fctx)
55 );
56}
[1141c1a]57
[f76fed4]58void fpu_init()
[3396f59]59{
[ffc277e]60 /* TODO: Zero all SSE, MMX etc. registers */
[3396f59]61 __asm__ volatile (
62 "fninit;"
63 );
64}
[b45c443]65
66 /** @}
67 */
68
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