source: mainline/kernel/arch/amd64/src/ddi/ddi.c@ 3eebe571

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3eebe571 was 6eeb4a3, checked in by Jakub Jermar <jakub@…>, 11 years ago

Deduplicate ddi_iospace_enable/disable_arch() code.

  • Property mode set to 100644
File size: 3.4 KB
RevLine 
[f52e54da]1/*
[df4ed85]2 * Copyright (c) 2006 Jakub Jermar
[f52e54da]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup amd64ddi
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f52e54da]35#include <ddi/ddi.h>
[2382d09]36#include <arch/ddi/ddi.h>
[f52e54da]37#include <proc/task.h>
[d99c1d2]38#include <typedefs.h>
[73e9b49]39#include <adt/bitmap.h>
40#include <mm/slab.h>
41#include <arch/pm.h>
42#include <errno.h>
[c7c0b89b]43#include <arch/cpu.h>
[7de18418]44#include <cpu.h>
[2382d09]45#include <arch.h>
[ea199e5]46#include <align.h>
[f52e54da]47
[2382d09]48/** Install I/O Permission bitmap.
49 *
50 * Current task's I/O permission bitmap, if any, is installed
51 * in the current CPU's TSS.
52 *
53 * Interrupts must be disabled prior this call.
[da1bafb]54 *
[2382d09]55 */
56void io_perm_bitmap_install(void)
57{
58 /* First, copy the I/O Permission Bitmap. */
[da1bafb]59 irq_spinlock_lock(&TASK->lock, false);
[7de18418]60
[da1bafb]61 size_t ver = TASK->arch.iomapver;
[7de18418]62 size_t elements = TASK->arch.iomap.elements;
63
64 if (elements > 0) {
65 ASSERT(TASK->arch.iomap.bits);
[da1bafb]66
67 bitmap_t iomap;
[c5396c1]68 bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8,
[7de18418]69 CPU->arch.tss->iomap);
70 bitmap_copy(&iomap, &TASK->arch.iomap, elements);
[da1bafb]71
[e9e5b9ab]72 /*
73 * Set the trailing bits in the last byte of the map to disable
74 * I/O access.
75 */
[7de18418]76 bitmap_set_range(&iomap, elements,
77 ALIGN_UP(elements, 8) - elements);
78
[2382d09]79 /*
[25b9e2c]80 * It is safe to set the trailing eight bits because of the
81 * extra convenience byte in TSS_IOMAP_SIZE.
[2382d09]82 */
[7de18418]83 bitmap_set_range(&iomap, ALIGN_UP(elements, 8), 8);
[2382d09]84 }
[7de18418]85
[da1bafb]86 irq_spinlock_unlock(&TASK->lock, false);
[99d6fd0]87
[ea199e5]88 /*
89 * Second, adjust TSS segment limit.
[7de18418]90 * Take the extra ending byte with all bits set into account.
[ea199e5]91 */
[da1bafb]92 ptr_16_64_t cpugdtr;
[2382d09]93 gdtr_store(&cpugdtr);
[da1bafb]94
95 descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base;
[c5396c1]96 size_t size = bitmap_size(elements);
[7de18418]97 gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size);
[2382d09]98 gdtr_load(&cpugdtr);
99
100 /*
[99d6fd0]101 * Before we load new TSS limit, the current TSS descriptor
102 * type must be changed to describe inactive TSS.
103 */
[da1bafb]104 tss_descriptor_t *tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES];
[2382d09]105 tss_desc->type = AR_TSS;
[1d3d2cf]106 tr_load(GDT_SELECTOR(TSS_DES));
[2382d09]107
108 /*
109 * Update the generation count so that faults caused by
110 * early accesses can be serviced.
111 */
112 CPU->arch.iomapver_copy = ver;
113}
[b45c443]114
[06e1e95]115/** @}
[b45c443]116 */
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