| 1 | /*
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| 2 | * Copyright (c) 2001-2004 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup amd64
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #include <cpu.h>
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| 36 | #include <arch/cpu.h>
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| 37 | #include <arch/cpuid.h>
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| 38 | #include <arch/pm.h>
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| 39 |
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| 40 | #include <arch.h>
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| 41 | #include <print.h>
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| 42 | #include <fpu_context.h>
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| 43 |
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| 44 | /*
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| 45 | * Identification of CPUs.
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| 46 | * Contains only non-MP-Specification specific SMP code.
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| 47 | */
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| 48 | #define AMD_CPUID_EBX UINT32_C(0x68747541)
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| 49 | #define AMD_CPUID_ECX UINT32_C(0x444d4163)
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| 50 | #define AMD_CPUID_EDX UINT32_C(0x69746e65)
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| 51 |
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| 52 | #define INTEL_CPUID_EBX UINT32_C(0x756e6547)
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| 53 | #define INTEL_CPUID_ECX UINT32_C(0x6c65746e)
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| 54 | #define INTEL_CPUID_EDX UINT32_C(0x49656e69)
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| 55 |
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| 56 | enum vendor {
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| 57 | VendorUnknown = 0,
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| 58 | VendorAMD,
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| 59 | VendorIntel
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| 60 | };
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| 61 |
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| 62 | static const char *vendor_str[] = {
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| 63 | "Unknown Vendor",
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| 64 | "AuthenticAMD",
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| 65 | "GenuineIntel"
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| 66 | };
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| 67 |
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| 68 |
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| 69 | /** Setup flags on processor so that we can use the FPU
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| 70 | *
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| 71 | * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
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| 72 | * cr0.em = 0 -> we do not emulate coprocessor
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| 73 | * cr0.mp = 1 -> we do want lazy context switch
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| 74 | */
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| 75 | void cpu_setup_fpu(void)
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| 76 | {
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| 77 | write_cr0((read_cr0() & ~CR0_EM) | CR0_MP);
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| 78 | write_cr4(read_cr4() | CR4_OSFXSR);
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| 79 | }
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| 80 |
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| 81 | /** Set the TS flag to 1.
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| 82 | *
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| 83 | * If a thread accesses coprocessor, exception is run, which
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| 84 | * does a lazy fpu context switch.
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| 85 | *
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| 86 | */
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| 87 | void fpu_disable(void)
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| 88 | {
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| 89 | write_cr0(read_cr0() | CR0_TS);
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| 90 | }
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| 91 |
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| 92 | void fpu_enable(void)
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| 93 | {
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| 94 | write_cr0(read_cr0() & ~CR0_TS);
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| 95 | }
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| 96 |
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| 97 | void cpu_arch_init(void)
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| 98 | {
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| 99 | CPU->arch.tss = tss_p;
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| 100 | CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] -
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| 101 | ((uint8_t *) CPU->arch.tss);
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| 102 | CPU->fpu_owner = NULL;
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| 103 | }
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| 104 |
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| 105 | void cpu_identify(void)
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| 106 | {
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| 107 | cpu_info_t info;
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| 108 |
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| 109 | CPU->arch.vendor = VendorUnknown;
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| 110 | if (has_cpuid()) {
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| 111 | cpuid(INTEL_CPUID_LEVEL, &info);
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| 112 |
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| 113 | /*
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| 114 | * Check for AMD processor.
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| 115 | */
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| 116 | if ((info.cpuid_ebx == AMD_CPUID_EBX) &&
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| 117 | (info.cpuid_ecx == AMD_CPUID_ECX) &&
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| 118 | (info.cpuid_edx == AMD_CPUID_EDX)) {
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| 119 | CPU->arch.vendor = VendorAMD;
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| 120 | }
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| 121 |
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| 122 | /*
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| 123 | * Check for Intel processor.
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| 124 | */
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| 125 | if ((info.cpuid_ebx == INTEL_CPUID_EBX) &&
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| 126 | (info.cpuid_ecx == INTEL_CPUID_ECX) &&
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| 127 | (info.cpuid_edx == INTEL_CPUID_EDX)) {
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| 128 | CPU->arch.vendor = VendorIntel;
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| 129 | }
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| 130 |
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| 131 | cpuid(INTEL_CPUID_STANDARD, &info);
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| 132 | CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
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| 133 | CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;
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| 134 | CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf;
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| 135 | }
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| 136 | }
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| 137 |
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| 138 | void cpu_print_report(cpu_t* m)
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| 139 | {
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| 140 | printf("cpu%d: (%s family=%d model=%d stepping=%d apicid=%u) %dMHz\n",
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| 141 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
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| 142 | m->arch.stepping, m->arch.id, m->frequency_mhz);
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| 143 | }
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| 144 |
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| 145 | /** @}
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| 146 | */
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