source: mainline/kernel/arch/amd64/src/cpu/cpu.c@ 9ef1fade

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9ef1fade was 83dab11, checked in by Jiri Svoboda <jiri@…>, 8 years ago

Replace usage of typedefs.h with includes of more specific, standard headers, where applicable.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 */
34
35#include <cpu.h>
36#include <arch/cpu.h>
37#include <arch/cpuid.h>
38#include <arch/pm.h>
39
40#include <arch.h>
41#include <print.h>
42#include <fpu_context.h>
43
44/*
45 * Identification of CPUs.
46 * Contains only non-MP-Specification specific SMP code.
47 */
48#define AMD_CPUID_EBX UINT32_C(0x68747541)
49#define AMD_CPUID_ECX UINT32_C(0x444d4163)
50#define AMD_CPUID_EDX UINT32_C(0x69746e65)
51
52#define INTEL_CPUID_EBX UINT32_C(0x756e6547)
53#define INTEL_CPUID_ECX UINT32_C(0x6c65746e)
54#define INTEL_CPUID_EDX UINT32_C(0x49656e69)
55
56enum vendor {
57 VendorUnknown = 0,
58 VendorAMD,
59 VendorIntel
60};
61
62static const char *vendor_str[] = {
63 "Unknown Vendor",
64 "AuthenticAMD",
65 "GenuineIntel"
66};
67
68
69/** Setup flags on processor so that we can use the FPU
70 *
71 * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
72 * cr0.em = 0 -> we do not emulate coprocessor
73 * cr0.mp = 1 -> we do want lazy context switch
74 */
75void cpu_setup_fpu(void)
76{
77 write_cr0((read_cr0() & ~CR0_EM) | CR0_MP);
78 write_cr4(read_cr4() | CR4_OSFXSR);
79}
80
81/** Set the TS flag to 1.
82 *
83 * If a thread accesses coprocessor, exception is run, which
84 * does a lazy fpu context switch.
85 *
86 */
87void fpu_disable(void)
88{
89 write_cr0(read_cr0() | CR0_TS);
90}
91
92void fpu_enable(void)
93{
94 write_cr0(read_cr0() & ~CR0_TS);
95}
96
97void cpu_arch_init(void)
98{
99 CPU->arch.tss = tss_p;
100 CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] -
101 ((uint8_t *) CPU->arch.tss);
102 CPU->fpu_owner = NULL;
103}
104
105void cpu_identify(void)
106{
107 cpu_info_t info;
108
109 CPU->arch.vendor = VendorUnknown;
110 if (has_cpuid()) {
111 cpuid(INTEL_CPUID_LEVEL, &info);
112
113 /*
114 * Check for AMD processor.
115 */
116 if ((info.cpuid_ebx == AMD_CPUID_EBX) &&
117 (info.cpuid_ecx == AMD_CPUID_ECX) &&
118 (info.cpuid_edx == AMD_CPUID_EDX)) {
119 CPU->arch.vendor = VendorAMD;
120 }
121
122 /*
123 * Check for Intel processor.
124 */
125 if ((info.cpuid_ebx == INTEL_CPUID_EBX) &&
126 (info.cpuid_ecx == INTEL_CPUID_ECX) &&
127 (info.cpuid_edx == INTEL_CPUID_EDX)) {
128 CPU->arch.vendor = VendorIntel;
129 }
130
131 cpuid(INTEL_CPUID_STANDARD, &info);
132 CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
133 CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;
134 CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf;
135 }
136}
137
138void cpu_print_report(cpu_t* m)
139{
140 printf("cpu%d: (%s family=%d model=%d stepping=%d apicid=%u) %dMHz\n",
141 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
142 m->arch.stepping, m->arch.id, m->frequency_mhz);
143}
144
145/** @}
146 */
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