source: mainline/kernel/arch/amd64/src/cpu/cpu.c@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was 33eb919, checked in by Jakub Jermar <jakub@…>, 16 years ago

Use defined macros instead of magic constants.

  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 */
34
35#include <cpu.h>
36#include <arch/cpu.h>
37#include <arch/cpuid.h>
38#include <arch/pm.h>
39
40#include <arch.h>
41#include <arch/types.h>
42#include <print.h>
43#include <fpu_context.h>
44
45/*
46 * Identification of CPUs.
47 * Contains only non-MP-Specification specific SMP code.
48 */
49#define AMD_CPUID_EBX 0x68747541
50#define AMD_CPUID_ECX 0x444d4163
51#define AMD_CPUID_EDX 0x69746e65
52
53#define INTEL_CPUID_EBX 0x756e6547
54#define INTEL_CPUID_ECX 0x6c65746e
55#define INTEL_CPUID_EDX 0x49656e69
56
57
58enum vendor {
59 VendorUnknown = 0,
60 VendorAMD,
61 VendorIntel
62};
63
64static char *vendor_str[] = {
65 "Unknown Vendor",
66 "AuthenticAMD",
67 "GenuineIntel"
68};
69
70
71/** Setup flags on processor so that we can use the FPU
72 *
73 * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
74 * cr0.em = 0 -> we do not emulate coprocessor
75 * cr0.mp = 1 -> we do want lazy context switch
76 */
77void cpu_setup_fpu(void)
78{
79 asm volatile (
80 "movq %%cr0, %%rax\n"
81 "btsq $1, %%rax\n" /* cr0.mp */
82 "btrq $2, %%rax\n" /* cr0.em */
83 "movq %%rax, %%cr0\n"
84
85 "movq %%cr4, %%rax\n"
86 "bts $9, %%rax\n" /* cr4.osfxsr */
87 "movq %%rax, %%cr4\n"
88 ::: "%rax"
89 );
90}
91
92/** Set the TS flag to 1.
93 *
94 * If a thread accesses coprocessor, exception is run, which
95 * does a lazy fpu context switch.
96 *
97 */
98void fpu_disable(void)
99{
100 asm volatile (
101 "mov %%cr0, %%rax\n"
102 "bts $3, %%rax\n"
103 "mov %%rax, %%cr0\n"
104 ::: "%rax"
105 );
106}
107
108void fpu_enable(void)
109{
110 asm volatile (
111 "mov %%cr0, %%rax\n"
112 "btr $3, %%rax\n"
113 "mov %%rax, %%cr0\n"
114 ::: "%rax"
115 );
116}
117
118void cpu_arch_init(void)
119{
120 CPU->arch.tss = tss_p;
121 CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] -
122 ((uint8_t *) CPU->arch.tss);
123 CPU->fpu_owner = NULL;
124}
125
126void cpu_identify(void)
127{
128 cpu_info_t info;
129
130 CPU->arch.vendor = VendorUnknown;
131 if (has_cpuid()) {
132 cpuid(INTEL_CPUID_LEVEL, &info);
133
134 /*
135 * Check for AMD processor.
136 */
137 if (info.cpuid_ebx == AMD_CPUID_EBX &&
138 info.cpuid_ecx == AMD_CPUID_ECX &&
139 info.cpuid_edx == AMD_CPUID_EDX) {
140 CPU->arch.vendor = VendorAMD;
141 }
142
143 /*
144 * Check for Intel processor.
145 */
146 if (info.cpuid_ebx == INTEL_CPUID_EBX &&
147 info.cpuid_ecx == INTEL_CPUID_ECX &&
148 info.cpuid_edx == INTEL_CPUID_EDX) {
149 CPU->arch.vendor = VendorIntel;
150 }
151
152 cpuid(INTEL_CPUID_STANDARD, &info);
153 CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
154 CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;
155 CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf;
156 }
157}
158
159void cpu_print_report(cpu_t* m)
160{
161 printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
162 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
163 m->arch.stepping, m->frequency_mhz);
164}
165
166/** @}
167 */
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