source: mainline/kernel/arch/amd64/src/cpu/cpu.c@ 525c5ac

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 525c5ac was 811770c, checked in by Jakub Jermar <jakub@…>, 9 years ago

Avoid magic numbers and specialized functions to set/get register bits

  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 */
34
35#include <cpu.h>
36#include <arch/cpu.h>
37#include <arch/cpuid.h>
38#include <arch/pm.h>
39
40#include <arch.h>
41#include <typedefs.h>
42#include <print.h>
43#include <fpu_context.h>
44
45/*
46 * Identification of CPUs.
47 * Contains only non-MP-Specification specific SMP code.
48 */
49#define AMD_CPUID_EBX UINT32_C(0x68747541)
50#define AMD_CPUID_ECX UINT32_C(0x444d4163)
51#define AMD_CPUID_EDX UINT32_C(0x69746e65)
52
53#define INTEL_CPUID_EBX UINT32_C(0x756e6547)
54#define INTEL_CPUID_ECX UINT32_C(0x6c65746e)
55#define INTEL_CPUID_EDX UINT32_C(0x49656e69)
56
57enum vendor {
58 VendorUnknown = 0,
59 VendorAMD,
60 VendorIntel
61};
62
63static const char *vendor_str[] = {
64 "Unknown Vendor",
65 "AuthenticAMD",
66 "GenuineIntel"
67};
68
69
70/** Setup flags on processor so that we can use the FPU
71 *
72 * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
73 * cr0.em = 0 -> we do not emulate coprocessor
74 * cr0.mp = 1 -> we do want lazy context switch
75 */
76void cpu_setup_fpu(void)
77{
78 write_cr0((read_cr0() & ~CR0_EM) | CR0_MP);
79 write_cr4(read_cr4() | CR4_OSFXSR);
80}
81
82/** Set the TS flag to 1.
83 *
84 * If a thread accesses coprocessor, exception is run, which
85 * does a lazy fpu context switch.
86 *
87 */
88void fpu_disable(void)
89{
90 write_cr0(read_cr0() | CR0_TS);
91}
92
93void fpu_enable(void)
94{
95 write_cr0(read_cr0() & ~CR0_TS);
96}
97
98void cpu_arch_init(void)
99{
100 CPU->arch.tss = tss_p;
101 CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] -
102 ((uint8_t *) CPU->arch.tss);
103 CPU->fpu_owner = NULL;
104}
105
106void cpu_identify(void)
107{
108 cpu_info_t info;
109
110 CPU->arch.vendor = VendorUnknown;
111 if (has_cpuid()) {
112 cpuid(INTEL_CPUID_LEVEL, &info);
113
114 /*
115 * Check for AMD processor.
116 */
117 if ((info.cpuid_ebx == AMD_CPUID_EBX) &&
118 (info.cpuid_ecx == AMD_CPUID_ECX) &&
119 (info.cpuid_edx == AMD_CPUID_EDX)) {
120 CPU->arch.vendor = VendorAMD;
121 }
122
123 /*
124 * Check for Intel processor.
125 */
126 if ((info.cpuid_ebx == INTEL_CPUID_EBX) &&
127 (info.cpuid_ecx == INTEL_CPUID_ECX) &&
128 (info.cpuid_edx == INTEL_CPUID_EDX)) {
129 CPU->arch.vendor = VendorIntel;
130 }
131
132 cpuid(INTEL_CPUID_STANDARD, &info);
133 CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
134 CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;
135 CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf;
136 }
137}
138
139void cpu_print_report(cpu_t* m)
140{
141 printf("cpu%d: (%s family=%d model=%d stepping=%d apicid=%u) %dMHz\n",
142 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
143 m->arch.stepping, m->arch.id, m->frequency_mhz);
144}
145
146/** @}
147 */
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