| 1 | #
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| 2 | # Copyright (C) 2005 Ondrej Palkovsky
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | #define IREGISTER_SPACE 120
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| 30 |
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| 31 | #define IOFFSET_RAX 0x0
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| 32 | #define IOFFSET_RBX 0x8
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| 33 | #define IOFFSET_RCX 0x10
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| 34 | #define IOFFSET_RDX 0x18
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| 35 | #define IOFFSET_RSI 0x20
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| 36 | #define IOFFSET_RDI 0x28
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| 37 | #define IOFFSET_R8 0x30
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| 38 | #define IOFFSET_R9 0x38
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| 39 | #define IOFFSET_R10 0x40
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| 40 | #define IOFFSET_R11 0x48
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| 41 | #define IOFFSET_R12 0x50
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| 42 | #define IOFFSET_R13 0x58
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| 43 | #define IOFFSET_R14 0x60
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| 44 | #define IOFFSET_R15 0x68
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| 45 | #define IOFFSET_RBP 0x70
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| 46 |
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| 47 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
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| 48 | # and 1 means interrupt with error word
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| 49 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00
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| 50 |
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| 51 | #include <arch/pm.h>
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| 52 | #include <arch/mm/page.h>
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| 53 |
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| 54 | .text
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| 55 | .global interrupt_handlers
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| 56 | .global syscall_entry
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| 57 | .global panic_printf
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| 58 |
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| 59 | panic_printf:
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| 60 | movq $halt, (%rsp)
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| 61 | jmp printf
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| 62 |
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| 63 | .global cpuid
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| 64 | .global has_cpuid
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| 65 | .global rdtsc
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| 66 | .global read_efer_flag
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| 67 | .global set_efer_flag
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| 68 | .global memcpy
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| 69 | .global memcpy_from_uspace
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| 70 | .global memcpy_to_uspace
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| 71 | .global memcpy_from_uspace_failover_address
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| 72 | .global memcpy_to_uspace_failover_address
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| 73 |
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| 74 | #define MEMCPY_DST %rdi
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| 75 | #define MEMCPY_SRC %rsi
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| 76 | #define MEMCPY_SIZE %rdx
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| 77 |
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| 78 | /**
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| 79 | * Copy memory from/to userspace.
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| 80 | *
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| 81 | * This is almost conventional memcpy().
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| 82 | * The difference is that there is a failover part
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| 83 | * to where control is returned from a page fault if
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| 84 | * the page fault occurs during copy_from_uspace()
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| 85 | * or copy_to_uspace().
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| 86 | *
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| 87 | * @param MEMCPY_DST Destination address.
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| 88 | * @param MEMCPY_SRC Source address.
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| 89 | * @param MEMCPY_SIZE Number of bytes to copy.
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| 90 | *
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| 91 | * @retrun MEMCPY_SRC on success, 0 on failure.
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| 92 | */
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| 93 | memcpy:
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| 94 | memcpy_from_uspace:
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| 95 | memcpy_to_uspace:
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| 96 | movq MEMCPY_SRC, %rax
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| 97 |
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| 98 | movq MEMCPY_SIZE, %rcx
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| 99 | shrq $3, %rcx /* size / 8 */
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| 100 |
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| 101 | rep movsq /* copy as much as possible word by word */
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| 102 |
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| 103 | movq MEMCPY_SIZE, %rcx
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| 104 | andq $7, %rcx /* size % 8 */
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| 105 | jz 0f
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| 106 |
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| 107 | rep movsb /* copy the rest byte by byte */
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| 108 |
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| 109 | 0:
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| 110 | ret /* return MEMCPY_SRC, success */
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| 111 |
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| 112 | memcpy_from_uspace_failover_address:
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| 113 | memcpy_to_uspace_failover_address:
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| 114 | xorq %rax, %rax /* return 0, failure */
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| 115 | ret
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| 116 |
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| 117 | ## Determine CPUID support
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| 118 | #
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| 119 | # Return 0 in EAX if CPUID is not support, 1 if supported.
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| 120 | #
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| 121 | has_cpuid:
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| 122 | pushfq # store flags
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| 123 | popq %rax # read flags
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| 124 | movq %rax,%rdx # copy flags
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| 125 | btcl $21,%edx # swap the ID bit
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| 126 | pushq %rdx
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| 127 | popfq # propagate the change into flags
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| 128 | pushfq
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| 129 | popq %rdx # read flags
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| 130 | andl $(1<<21),%eax # interested only in ID bit
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| 131 | andl $(1<<21),%edx
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| 132 | xorl %edx,%eax # 0 if not supported, 1 if supported
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| 133 | ret
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| 134 |
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| 135 | cpuid:
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| 136 | movq %rbx, %r10 # we have to preserve rbx across function calls
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| 137 |
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| 138 | movl %edi,%eax # load the command into %eax
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| 139 |
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| 140 | cpuid
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| 141 | movl %eax,0(%rsi)
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| 142 | movl %ebx,4(%rsi)
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| 143 | movl %ecx,8(%rsi)
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| 144 | movl %edx,12(%rsi)
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| 145 |
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| 146 | movq %r10, %rbx
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| 147 | ret
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| 148 |
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| 149 | rdtsc:
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| 150 | xorq %rax,%rax
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| 151 | rdtsc
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| 152 | ret
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| 153 |
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| 154 | set_efer_flag:
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| 155 | movq $0xc0000080, %rcx
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| 156 | rdmsr
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| 157 | btsl %edi, %eax
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| 158 | wrmsr
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| 159 | ret
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| 160 |
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| 161 | read_efer_flag:
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| 162 | movq $0xc0000080, %rcx
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| 163 | rdmsr
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| 164 | ret
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| 165 |
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| 166 | # Push all general purpose registers on stack except %rbp, %rsp
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| 167 | .macro save_all_gpr
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| 168 | movq %rax, IOFFSET_RAX(%rsp)
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| 169 | movq %rcx, IOFFSET_RCX(%rsp)
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| 170 | movq %rdx, IOFFSET_RDX(%rsp)
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| 171 | movq %rsi, IOFFSET_RSI(%rsp)
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| 172 | movq %rdi, IOFFSET_RDI(%rsp)
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| 173 | movq %r8, IOFFSET_R8(%rsp)
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| 174 | movq %r9, IOFFSET_R9(%rsp)
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| 175 | movq %r10, IOFFSET_R10(%rsp)
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| 176 | movq %r11, IOFFSET_R11(%rsp)
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| 177 | #ifdef CONFIG_DEBUG_ALLREGS
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| 178 | movq %rbx, IOFFSET_RBX(%rsp)
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| 179 | movq %rbp, IOFFSET_RBP(%rsp)
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| 180 | movq %r12, IOFFSET_R12(%rsp)
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| 181 | movq %r13, IOFFSET_R13(%rsp)
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| 182 | movq %r14, IOFFSET_R14(%rsp)
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| 183 | movq %r15, IOFFSET_R15(%rsp)
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| 184 | #endif
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| 185 | .endm
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| 186 |
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| 187 | .macro restore_all_gpr
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| 188 | movq IOFFSET_RAX(%rsp), %rax
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| 189 | movq IOFFSET_RCX(%rsp), %rcx
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| 190 | movq IOFFSET_RDX(%rsp), %rdx
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| 191 | movq IOFFSET_RSI(%rsp), %rsi
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| 192 | movq IOFFSET_RDI(%rsp), %rdi
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| 193 | movq IOFFSET_R8(%rsp), %r8
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| 194 | movq IOFFSET_R9(%rsp), %r9
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| 195 | movq IOFFSET_R10(%rsp), %r10
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| 196 | movq IOFFSET_R11(%rsp), %r11
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| 197 | #ifdef CONFIG_DEBUG_ALLREGS
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| 198 | movq IOFFSET_RBX(%rsp), %rbx
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| 199 | movq IOFFSET_RBP(%rsp), %rbp
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| 200 | movq IOFFSET_R12(%rsp), %r12
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| 201 | movq IOFFSET_R13(%rsp), %r13
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| 202 | movq IOFFSET_R14(%rsp), %r14
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| 203 | movq IOFFSET_R15(%rsp), %r15
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| 204 | #endif
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| 205 | .endm
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| 206 |
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| 207 | #ifdef CONFIG_DEBUG_ALLREGS
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| 208 | # define INTERRUPT_ALIGN 256
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| 209 | #else
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| 210 | # define INTERRUPT_ALIGN 128
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| 211 | #endif
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| 212 |
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| 213 | ## Declare interrupt handlers
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| 214 | #
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| 215 | # Declare interrupt handlers for n interrupt
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| 216 | # vectors starting at vector i.
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| 217 | #
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| 218 | # The handlers call exc_dispatch().
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| 219 | #
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| 220 | .macro handler i n
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| 221 |
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| 222 | /*
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| 223 | * Choose between version with error code and version without error code.
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| 224 | * Both versions have to be of the same size. amd64 assembly is, however,
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| 225 | * a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp
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| 226 | * can result in two instructions with different op-code lengths.
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| 227 | * Therefore we align the interrupt handlers.
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| 228 | */
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| 229 |
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| 230 | .iflt \i-32
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| 231 | .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
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| 232 | /*
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| 233 | * Version with error word.
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| 234 | */
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| 235 | subq $IREGISTER_SPACE, %rsp
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| 236 | .else
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| 237 | /*
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| 238 | * Version without error word,
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| 239 | */
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| 240 | subq $(IREGISTER_SPACE+8), %rsp
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| 241 | .endif
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| 242 | .else
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| 243 | /*
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| 244 | * Version without error word,
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| 245 | */
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| 246 | subq $(IREGISTER_SPACE+8), %rsp
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| 247 | .endif
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| 248 |
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| 249 | save_all_gpr
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| 250 |
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| 251 | movq $(\i), %rdi # %rdi - first parameter
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| 252 | movq %rsp, %rsi # %rsi - pointer to istate
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| 253 | call exc_dispatch # exc_dispatch(i, istate)
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| 254 |
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| 255 | restore_all_gpr
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| 256 | # $8 = Skip error word
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| 257 | addq $(IREGISTER_SPACE+8), %rsp
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| 258 | iretq
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| 259 |
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| 260 | .align INTERRUPT_ALIGN
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| 261 | .if (\n-\i)-1
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| 262 | handler "(\i+1)",\n
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| 263 | .endif
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| 264 | .endm
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| 265 |
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| 266 | .align INTERRUPT_ALIGN
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| 267 | interrupt_handlers:
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| 268 | h_start:
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| 269 | handler 0 IDT_ITEMS
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| 270 | h_end:
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| 271 |
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| 272 |
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| 273 | syscall_entry:
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| 274 | # Switch to hidden gs
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| 275 | swapgs
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| 276 | # %gs:0 now points to pointer to stack page
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| 277 | mov %gs:0, %r10 # We have a ptr to stack page in r10
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| 278 | addq $PAGE_SIZE-16, %r10 # We need some space to store old %sp
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| 279 |
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| 280 | movq %rsp, 0(%r10) # Save old stack pointer to stack
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| 281 | movq %r10, %rsp # Change to new stack
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| 282 | pushq %rcx # Return address
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| 283 | pushq %r11 # Save flags
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| 284 |
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| 285 | # Switch back to remain consistent
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| 286 | swapgs
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| 287 |
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| 288 | sti
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| 289 | movq %r9, %rcx # Exchange last parameter as a third
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| 290 |
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| 291 | call syscall_handler
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| 292 | cli # We will be touching stack pointer
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| 293 |
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| 294 | popq %r11
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| 295 | popq %rcx
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| 296 | movq 0(%rsp), %rsp
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| 297 | sysretq
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| 298 |
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| 299 |
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| 300 | .data
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| 301 | .global interrupt_handler_size
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| 302 |
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| 303 | interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS
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