source: mainline/kernel/arch/amd64/src/amd64.c@ d8bb821

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d8bb821 was 3da166f0, checked in by Jakub Jermar <jakub@…>, 11 years ago

Merge from lp:~martin-sucha/helenos/kernel-serial
  • Property mode set to 100644
File size: 7.2 KB
Line 
1/*
2 * Copyright (c) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36#include <typedefs.h>
37#include <errno.h>
38#include <memstr.h>
39#include <interrupt.h>
40#include <console/console.h>
41#include <syscall/syscall.h>
42#include <sysinfo/sysinfo.h>
43#include <arch/bios/bios.h>
44#include <arch/boot/boot.h>
45#include <arch/drivers/i8254.h>
46#include <arch/drivers/i8259.h>
47#include <arch/syscall.h>
48#include <genarch/acpi/acpi.h>
49#include <genarch/drivers/ega/ega.h>
50#include <genarch/drivers/i8042/i8042.h>
51#include <genarch/drivers/ns16550/ns16550.h>
52#include <genarch/drivers/legacy/ia32/io.h>
53#include <genarch/fb/bfb.h>
54#include <genarch/kbrd/kbrd.h>
55#include <genarch/srln/srln.h>
56#include <genarch/multiboot/multiboot.h>
57#include <genarch/multiboot/multiboot2.h>
58
59#ifdef CONFIG_SMP
60#include <arch/smp/apic.h>
61#endif
62
63/** Disable I/O on non-privileged levels
64 *
65 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
66 */
67static void clean_IOPL_NT_flags(void)
68{
69 asm volatile (
70 "pushfq\n"
71 "pop %%rax\n"
72 "and $~(0x7000), %%rax\n"
73 "pushq %%rax\n"
74 "popfq\n"
75 ::: "%rax"
76 );
77}
78
79/** Disable alignment check
80 *
81 * Clean AM(18) flag in CR0 register
82 */
83static void clean_AM_flag(void)
84{
85 asm volatile (
86 "mov %%cr0, %%rax\n"
87 "and $~(0x40000), %%rax\n"
88 "mov %%rax, %%cr0\n"
89 ::: "%rax"
90 );
91}
92
93/** Perform amd64-specific initialization before main_bsp() is called.
94 *
95 * @param signature Multiboot signature.
96 * @param info Multiboot information structure.
97 *
98 */
99void arch_pre_main(uint32_t signature, void *info)
100{
101 /* Parse multiboot information obtained from the bootloader. */
102 multiboot_info_parse(signature, (multiboot_info_t *) info);
103 multiboot2_info_parse(signature, (multiboot2_info_t *) info);
104
105#ifdef CONFIG_SMP
106 /* Copy AP bootstrap routines below 1 MB. */
107 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
108 (size_t) &_hardcoded_unmapped_size);
109#endif
110}
111
112void arch_pre_mm_init(void)
113{
114 /* Enable no-execute pages */
115 set_efer_flag(AMD_NXE_FLAG);
116 /* Enable FPU */
117 cpu_setup_fpu();
118
119 /* Initialize segmentation */
120 pm_init();
121
122 /* Disable I/O on nonprivileged levels
123 * clear the NT (nested-thread) flag
124 */
125 clean_IOPL_NT_flags();
126 /* Disable alignment check */
127 clean_AM_flag();
128
129 if (config.cpu_active == 1) {
130 interrupt_init();
131 bios_init();
132
133 /* PIC */
134 i8259_init();
135 }
136}
137
138
139void arch_post_mm_init(void)
140{
141 if (config.cpu_active == 1) {
142 /* Initialize IRQ routing */
143 irq_init(IRQ_COUNT, IRQ_COUNT);
144
145 /* hard clock */
146 i8254_init();
147
148#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
149 bool bfb = false;
150#endif
151
152#ifdef CONFIG_FB
153 bfb = bfb_init();
154#endif
155
156#ifdef CONFIG_EGA
157 if (!bfb) {
158 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
159 if (egadev)
160 stdout_wire(egadev);
161 }
162#endif
163
164 /* Merge all memory zones to 1 big zone */
165 zone_merge_all();
166 }
167
168 /* Setup fast SYSCALL/SYSRET */
169 syscall_setup_cpu();
170}
171
172void arch_post_cpu_init()
173{
174#ifdef CONFIG_SMP
175 if (config.cpu_active > 1) {
176 l_apic_init();
177 l_apic_debug();
178 }
179#endif
180}
181
182void arch_pre_smp_init(void)
183{
184 if (config.cpu_active == 1) {
185#ifdef CONFIG_SMP
186 acpi_init();
187#endif /* CONFIG_SMP */
188 }
189}
190
191void arch_post_smp_init(void)
192{
193 /* Currently the only supported platform for amd64 is 'pc'. */
194 static const char *platform = "pc";
195
196 sysinfo_set_item_data("platform", NULL, (void *) platform,
197 str_size(platform));
198
199#ifdef CONFIG_PC_KBD
200 /*
201 * Initialize the i8042 controller. Then initialize the keyboard
202 * module and connect it to i8042. Enable keyboard interrupts.
203 */
204 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
205 if (i8042_instance) {
206 kbrd_instance_t *kbrd_instance = kbrd_init();
207 if (kbrd_instance) {
208 indev_t *sink = stdin_wire();
209 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
210 i8042_wire(i8042_instance, kbrd);
211 trap_virtual_enable_irqs(1 << IRQ_KBD);
212 trap_virtual_enable_irqs(1 << IRQ_MOUSE);
213 }
214 }
215#endif
216
217#if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
218 /*
219 * Initialize the ns16550 controller.
220 */
221#ifdef CONFIG_NS16550_OUT
222 outdev_t *ns16550_out;
223 outdev_t **ns16550_out_ptr = &ns16550_out;
224#else
225 outdev_t **ns16550_out_ptr = NULL;
226#endif
227 ns16550_instance_t *ns16550_instance
228 = ns16550_init((ns16550_t *) NS16550_BASE, IRQ_NS16550, NULL, NULL,
229 ns16550_out_ptr);
230 if (ns16550_instance) {
231#ifdef CONFIG_NS16550
232 srln_instance_t *srln_instance = srln_init();
233 if (srln_instance) {
234 indev_t *sink = stdin_wire();
235 indev_t *srln = srln_wire(srln_instance, sink);
236 ns16550_wire(ns16550_instance, srln);
237 trap_virtual_enable_irqs(1 << IRQ_NS16550);
238 }
239#endif
240#ifdef CONFIG_NS16550_OUT
241 if (ns16550_out) {
242 stdout_wire(ns16550_out);
243 }
244#endif
245 }
246#endif
247
248 if (irqs_info != NULL)
249 sysinfo_set_item_val(irqs_info, NULL, true);
250}
251
252void calibrate_delay_loop(void)
253{
254 i8254_calibrate_delay_loop();
255 if (config.cpu_active == 1) {
256 /*
257 * This has to be done only on UP.
258 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
259 */
260 i8254_normal_operation();
261 }
262}
263
264/** Set thread-local-storage pointer
265 *
266 * TLS pointer is set in FS register. Unfortunately the 64-bit
267 * part can be set only in CPL0 mode.
268 *
269 * The specs say, that on %fs:0 there is stored contents of %fs register,
270 * we need not to go to CPL0 to read it.
271 */
272sysarg_t sys_tls_set(uintptr_t addr)
273{
274 THREAD->arch.tls = addr;
275 write_msr(AMD_MSR_FS, addr);
276
277 return EOK;
278}
279
280/** Construct function pointer
281 *
282 * @param fptr function pointer structure
283 * @param addr function address
284 * @param caller calling function address
285 *
286 * @return address of the function pointer
287 *
288 */
289void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
290{
291 return addr;
292}
293
294void arch_reboot(void)
295{
296#ifdef CONFIG_PC_KBD
297 i8042_cpu_reset((i8042_t *) I8042_BASE);
298#endif
299}
300
301void irq_initialize_arch(irq_t *irq)
302{
303 (void) irq;
304}
305
306/** @}
307 */
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