source: mainline/kernel/arch/amd64/src/amd64.c@ 63660a3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 63660a3 was 2a103b5, checked in by Jakub Jermar <jakub@…>, 6 years ago

Introduce PIC operations indirection mechanism

Some architectures switch from one interrupt controller implementation
to another during runtime. By providing a cleaner indirection mechanism,
it is possible e.g. for the ia32 IRQ 7 handler to distinguish i8259
spurious interrupts from actual IRQ 7 device interrupts, even when the
i8259 interrupt controller is no longer active.

  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*
2 * Copyright (c) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_amd64
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36#include <arch/arch.h>
37#include <stdint.h>
38#include <errno.h>
39#include <mem.h>
40#include <interrupt.h>
41#include <console/console.h>
42#include <syscall/syscall.h>
43#include <sysinfo/sysinfo.h>
44#include <arch/bios/bios.h>
45#include <arch/boot/boot.h>
46#include <arch/drivers/i8254.h>
47#include <arch/syscall.h>
48#include <genarch/acpi/acpi.h>
49#include <genarch/drivers/ega/ega.h>
50#include <genarch/drivers/i8042/i8042.h>
51#include <genarch/drivers/i8259/i8259.h>
52#include <genarch/drivers/ns16550/ns16550.h>
53#include <genarch/drivers/legacy/ia32/io.h>
54#include <genarch/fb/bfb.h>
55#include <genarch/kbrd/kbrd.h>
56#include <genarch/srln/srln.h>
57#include <genarch/multiboot/multiboot.h>
58#include <genarch/multiboot/multiboot2.h>
59#include <arch/pm.h>
60#include <arch/vreg.h>
61#include <arch/kseg.h>
62#include <genarch/pic/pic_ops.h>
63
64#ifdef CONFIG_SMP
65#include <arch/smp/apic.h>
66#endif
67
68static void amd64_pre_mm_init(void);
69static void amd64_post_mm_init(void);
70static void amd64_post_cpu_init(void);
71static void amd64_pre_smp_init(void);
72static void amd64_post_smp_init(void);
73
74arch_ops_t amd64_ops = {
75 .pre_mm_init = amd64_pre_mm_init,
76 .post_mm_init = amd64_post_mm_init,
77 .post_cpu_init = amd64_post_cpu_init,
78 .pre_smp_init = amd64_pre_smp_init,
79 .post_smp_init = amd64_post_smp_init
80};
81
82arch_ops_t *arch_ops = &amd64_ops;
83
84/** Perform amd64-specific initialization before main_bsp() is called.
85 *
86 * @param signature Multiboot signature.
87 * @param info Multiboot information structure.
88 *
89 */
90void amd64_pre_main(uint32_t signature, void *info)
91{
92 /* Parse multiboot information obtained from the bootloader. */
93 multiboot_info_parse(signature, (multiboot_info_t *) info);
94 multiboot2_info_parse(signature, (multiboot2_info_t *) info);
95
96#ifdef CONFIG_SMP
97 size_t unmapped_size = (uintptr_t) unmapped_end - BOOT_OFFSET;
98 /* Copy AP bootstrap routines below 1 MB. */
99 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET, unmapped_size);
100#endif
101}
102
103void amd64_pre_mm_init(void)
104{
105 /* Enable no-execute pages */
106 write_msr(AMD_MSR_EFER, read_msr(AMD_MSR_EFER) | AMD_NXE);
107 /* Enable FPU */
108 cpu_setup_fpu();
109
110 /* Initialize segmentation */
111 pm_init();
112
113 /* Disable I/O on nonprivileged levels, clear the nested-thread flag */
114 write_rflags(read_rflags() & ~(RFLAGS_IOPL | RFLAGS_NT));
115 /* Disable alignment check */
116 write_cr0(read_cr0() & ~CR0_AM);
117
118 if (config.cpu_active == 1) {
119 interrupt_init();
120 bios_init();
121
122 /* PIC */
123 i8259_init((i8259_t *) I8259_PIC0_BASE,
124 (i8259_t *) I8259_PIC1_BASE, IVT_IRQBASE);
125
126 /* Set PIC operations. */
127 pic_ops = &i8259_pic_ops;
128 }
129}
130
131void amd64_post_mm_init(void)
132{
133 vreg_init();
134 kseg_init();
135
136 if (config.cpu_active == 1) {
137 /* Initialize IRQ routing */
138 irq_init(IRQ_COUNT, IRQ_COUNT);
139
140 /* hard clock */
141 i8254_init();
142
143#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
144 bool bfb = false;
145#endif
146
147#ifdef CONFIG_FB
148 bfb = bfb_init();
149#endif
150
151#ifdef CONFIG_EGA
152 if (!bfb) {
153 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
154 if (egadev)
155 stdout_wire(egadev);
156 }
157#endif
158
159 /* Merge all memory zones to 1 big zone */
160 zone_merge_all();
161 }
162
163 /* Setup fast SYSCALL/SYSRET */
164 syscall_setup_cpu();
165}
166
167void amd64_post_cpu_init(void)
168{
169#ifdef CONFIG_SMP
170 if (config.cpu_active > 1) {
171 l_apic_init();
172 l_apic_debug();
173 }
174#endif
175}
176
177void amd64_pre_smp_init(void)
178{
179 if (config.cpu_active == 1) {
180#ifdef CONFIG_SMP
181 acpi_init();
182#endif /* CONFIG_SMP */
183 }
184}
185
186void amd64_post_smp_init(void)
187{
188 /* Currently the only supported platform for amd64 is 'pc'. */
189 static const char *platform = "pc";
190
191 sysinfo_set_item_data("platform", NULL, (void *) platform,
192 str_size(platform));
193
194#ifdef CONFIG_PC_KBD
195 /*
196 * Initialize the i8042 controller. Then initialize the keyboard
197 * module and connect it to i8042. Enable keyboard interrupts.
198 */
199 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
200 if (i8042_instance) {
201 kbrd_instance_t *kbrd_instance = kbrd_init();
202 if (kbrd_instance) {
203 indev_t *sink = stdin_wire();
204 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
205 i8042_wire(i8042_instance, kbrd);
206 pic_ops->enable_irqs(1 << IRQ_KBD);
207 pic_ops->enable_irqs(1 << IRQ_MOUSE);
208 }
209 }
210#endif
211
212#if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
213 /*
214 * Initialize the ns16550 controller.
215 */
216#ifdef CONFIG_NS16550_OUT
217 outdev_t *ns16550_out;
218 outdev_t **ns16550_out_ptr = &ns16550_out;
219#else
220 outdev_t **ns16550_out_ptr = NULL;
221#endif
222 ns16550_instance_t *ns16550_instance =
223 ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
224 ns16550_out_ptr);
225 if (ns16550_instance) {
226#ifdef CONFIG_NS16550
227 srln_instance_t *srln_instance = srln_init();
228 if (srln_instance) {
229 indev_t *sink = stdin_wire();
230 indev_t *srln = srln_wire(srln_instance, sink);
231 ns16550_wire(ns16550_instance, srln);
232 pic_ops->enable_irqs(1 << IRQ_NS16550);
233 }
234#endif
235#ifdef CONFIG_NS16550_OUT
236 if (ns16550_out) {
237 stdout_wire(ns16550_out);
238 }
239#endif
240 }
241#endif
242
243 sysinfo_set_item_val(pic_ops->get_name(), NULL, true);
244}
245
246void calibrate_delay_loop(void)
247{
248 i8254_calibrate_delay_loop();
249 if (config.cpu_active == 1) {
250 /*
251 * This has to be done only on UP.
252 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
253 */
254 i8254_normal_operation();
255 }
256}
257
258/** Construct function pointer
259 *
260 * @param fptr function pointer structure
261 * @param addr function address
262 * @param caller calling function address
263 *
264 * @return address of the function pointer
265 *
266 */
267void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
268{
269 return addr;
270}
271
272void arch_reboot(void)
273{
274#ifdef CONFIG_PC_KBD
275 i8042_cpu_reset((i8042_t *) I8042_BASE);
276#endif
277}
278
279void irq_initialize_arch(irq_t *irq)
280{
281 (void) irq;
282}
283
284/** @}
285 */
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