source: mainline/kernel/arch/amd64/src/amd64.c@ fd67c9f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since fd67c9f was bbb99f82, checked in by Jakub Jermar <jakub@…>, 6 years ago

Remove last x86 specifics from i8259 kernel driver

  • Property mode set to 100644
File size: 7.3 KB
RevLine 
[b9e97fb]1/*
[df4ed85]2 * Copyright (c) 2005 Ondrej Palkovsky
[b9e97fb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[c5429fe]29/** @addtogroup kernel_amd64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[b9e97fb]35#include <arch.h>
[36df4109]36#include <arch/arch.h>
[83dab11]37#include <stdint.h>
[d8db519]38#include <errno.h>
[44a7ee5]39#include <mem.h>
[d8db519]40#include <interrupt.h>
41#include <console/console.h>
42#include <syscall/syscall.h>
43#include <sysinfo/sysinfo.h>
44#include <arch/bios/bios.h>
45#include <arch/boot/boot.h>
46#include <arch/drivers/i8254.h>
47#include <arch/syscall.h>
48#include <genarch/acpi/acpi.h>
[f245145]49#include <genarch/drivers/ega/ega.h>
[411b6a6]50#include <genarch/drivers/i8042/i8042.h>
[87a5796]51#include <genarch/drivers/i8259/i8259.h>
[3296df5]52#include <genarch/drivers/ns16550/ns16550.h>
[d8db519]53#include <genarch/drivers/legacy/ia32/io.h>
54#include <genarch/fb/bfb.h>
[411b6a6]55#include <genarch/kbrd/kbrd.h>
[3296df5]56#include <genarch/srln/srln.h>
[d8db519]57#include <genarch/multiboot/multiboot.h>
58#include <genarch/multiboot/multiboot2.h>
[1a5eca4]59#include <arch/pm.h>
60#include <arch/vreg.h>
61#include <arch/kseg.h>
[b9e97fb]62
[26678e5]63#ifdef CONFIG_SMP
64#include <arch/smp/apic.h>
65#endif
66
[36df4109]67static void amd64_pre_mm_init(void);
68static void amd64_post_mm_init(void);
69static void amd64_post_cpu_init(void);
70static void amd64_pre_smp_init(void);
71static void amd64_post_smp_init(void);
72
73arch_ops_t amd64_ops = {
74 .pre_mm_init = amd64_pre_mm_init,
75 .post_mm_init = amd64_post_mm_init,
76 .post_cpu_init = amd64_post_cpu_init,
77 .pre_smp_init = amd64_pre_smp_init,
78 .post_smp_init = amd64_post_smp_init
79};
80
81arch_ops_t *arch_ops = &amd64_ops;
82
[5d8d71e]83/** Perform amd64-specific initialization before main_bsp() is called.
84 *
[1f5c9c96]85 * @param signature Multiboot signature.
86 * @param info Multiboot information structure.
87 *
[5d8d71e]88 */
[36df4109]89void amd64_pre_main(uint32_t signature, void *info)
[5d8d71e]90{
91 /* Parse multiboot information obtained from the bootloader. */
[1f5c9c96]92 multiboot_info_parse(signature, (multiboot_info_t *) info);
93 multiboot2_info_parse(signature, (multiboot2_info_t *) info);
[a35b458]94
[5d8d71e]95#ifdef CONFIG_SMP
[bae43dc]96 size_t unmapped_size = (uintptr_t) unmapped_end - BOOT_OFFSET;
[5d8d71e]97 /* Copy AP bootstrap routines below 1 MB. */
[8a1afd2]98 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET, unmapped_size);
[5d8d71e]99#endif
100}
101
[36df4109]102void amd64_pre_mm_init(void)
[b9e97fb]103{
[4fb6bf36]104 /* Enable no-execute pages */
[811770c]105 write_msr(AMD_MSR_EFER, read_msr(AMD_MSR_EFER) | AMD_NXE);
[3396f59]106 /* Enable FPU */
107 cpu_setup_fpu();
[a35b458]108
[49a39c2]109 /* Initialize segmentation */
[b9e97fb]110 pm_init();
[a35b458]111
[811770c]112 /* Disable I/O on nonprivileged levels, clear the nested-thread flag */
113 write_rflags(read_rflags() & ~(RFLAGS_IOPL | RFLAGS_NT));
[49a39c2]114 /* Disable alignment check */
[811770c]115 write_cr0(read_cr0() & ~CR0_AM);
[a35b458]116
[b9e97fb]117 if (config.cpu_active == 1) {
[8607db8]118 interrupt_init();
[b9e97fb]119 bios_init();
[a35b458]120
[8607db8]121 /* PIC */
[d1cbad5]122 i8259_init((i8259_t *) I8259_PIC0_BASE,
[a773b8b]123 (i8259_t *) I8259_PIC1_BASE, IRQ_PIC1, IVT_IRQBASE,
124 IVT_IRQBASE + 8);
[bbb99f82]125
126 /*
127 * Set the enable/disable IRQs handlers.
128 * Set the End-of-Interrupt handler.
129 */
130 enable_irqs_function = pic_enable_irqs;
131 disable_irqs_function = pic_disable_irqs;
132 eoi_function = pic_eoi;
133 irqs_info = "i8259";
[b9e97fb]134 }
135}
136
[36df4109]137void amd64_post_mm_init(void)
[b9e97fb]138{
[1a5eca4]139 vreg_init();
140 kseg_init();
141
[b9e97fb]142 if (config.cpu_active == 1) {
[8607db8]143 /* Initialize IRQ routing */
144 irq_init(IRQ_COUNT, IRQ_COUNT);
[a35b458]145
[8607db8]146 /* hard clock */
147 i8254_init();
[a35b458]148
[a71c158]149#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
[1f5c9c96]150 bool bfb = false;
[a71c158]151#endif
[a35b458]152
[de07bcf]153#ifdef CONFIG_FB
[1f5c9c96]154 bfb = bfb_init();
[de07bcf]155#endif
[a35b458]156
[ec944b1]157#ifdef CONFIG_EGA
[1f5c9c96]158 if (!bfb) {
[a71c158]159 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
160 if (egadev)
161 stdout_wire(egadev);
162 }
[ec944b1]163#endif
[a35b458]164
[381465e]165 /* Merge all memory zones to 1 big zone */
166 zone_merge_all();
[b9e97fb]167 }
[a35b458]168
[dd4d6b0]169 /* Setup fast SYSCALL/SYSRET */
170 syscall_setup_cpu();
[b9e97fb]171}
[7df54df]172
[36df4109]173void amd64_post_cpu_init(void)
[26678e5]174{
175#ifdef CONFIG_SMP
176 if (config.cpu_active > 1) {
177 l_apic_init();
178 l_apic_debug();
179 }
180#endif
181}
182
[36df4109]183void amd64_pre_smp_init(void)
[7df54df]184{
185 if (config.cpu_active == 1) {
[0b5f9fa]186#ifdef CONFIG_SMP
[7df54df]187 acpi_init();
[0b5f9fa]188#endif /* CONFIG_SMP */
[7df54df]189 }
190}
191
[36df4109]192void amd64_post_smp_init(void)
[7453929]193{
[eff1f033]194 /* Currently the only supported platform for amd64 is 'pc'. */
195 static const char *platform = "pc";
196
197 sysinfo_set_item_data("platform", NULL, (void *) platform,
198 str_size(platform));
199
[4df7d3a]200#ifdef CONFIG_PC_KBD
201 /*
202 * Initialize the i8042 controller. Then initialize the keyboard
203 * module and connect it to i8042. Enable keyboard interrupts.
204 */
[c2417bc]205 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
206 if (i8042_instance) {
207 kbrd_instance_t *kbrd_instance = kbrd_init();
208 if (kbrd_instance) {
209 indev_t *sink = stdin_wire();
210 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
211 i8042_wire(i8042_instance, kbrd);
212 trap_virtual_enable_irqs(1 << IRQ_KBD);
[385a3d6]213 trap_virtual_enable_irqs(1 << IRQ_MOUSE);
[c2417bc]214 }
[4df7d3a]215 }
216#endif
[3296df5]217
[6bbe470]218#if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
[3296df5]219 /*
[6bbe470]220 * Initialize the ns16550 controller.
[3296df5]221 */
[21b6307]222#ifdef CONFIG_NS16550_OUT
223 outdev_t *ns16550_out;
224 outdev_t **ns16550_out_ptr = &ns16550_out;
225#else
226 outdev_t **ns16550_out_ptr = NULL;
227#endif
[3bacee1]228 ns16550_instance_t *ns16550_instance =
229 ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
[21b6307]230 ns16550_out_ptr);
[3296df5]231 if (ns16550_instance) {
[6bbe470]232#ifdef CONFIG_NS16550
[3296df5]233 srln_instance_t *srln_instance = srln_init();
234 if (srln_instance) {
235 indev_t *sink = stdin_wire();
236 indev_t *srln = srln_wire(srln_instance, sink);
237 ns16550_wire(ns16550_instance, srln);
[5030acad]238 trap_virtual_enable_irqs(1 << IRQ_NS16550);
[3296df5]239 }
240#endif
[6bbe470]241#ifdef CONFIG_NS16550_OUT
242 if (ns16550_out) {
243 stdout_wire(ns16550_out);
244 }
245#endif
[24b06199]246 }
247#endif
[a35b458]248
[acc7ce4]249 if (irqs_info != NULL)
250 sysinfo_set_item_val(irqs_info, NULL, true);
[7453929]251}
252
[7df54df]253void calibrate_delay_loop(void)
254{
255 i8254_calibrate_delay_loop();
[8607db8]256 if (config.cpu_active == 1) {
257 /*
258 * This has to be done only on UP.
259 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
260 */
261 i8254_normal_operation();
262 }
[7df54df]263}
[281b607]264
[6da1013f]265/** Construct function pointer
266 *
267 * @param fptr function pointer structure
268 * @param addr function address
269 * @param caller calling function address
270 *
271 * @return address of the function pointer
272 *
273 */
274void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
275{
276 return addr;
277}
278
[149d14e5]279void arch_reboot(void)
280{
281#ifdef CONFIG_PC_KBD
282 i8042_cpu_reset((i8042_t *) I8042_BASE);
283#endif
284}
285
[3a2f8aa]286void irq_initialize_arch(irq_t *irq)
287{
288 (void) irq;
289}
290
[287920f]291/** @}
[b45c443]292 */
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