[b9e97fb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2005 Ondrej Palkovsky
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[b9e97fb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[c5429fe] | 29 | /** @addtogroup kernel_amd64
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[b9e97fb] | 35 | #include <arch.h>
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[36df4109] | 36 | #include <arch/arch.h>
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[83dab11] | 37 | #include <stdint.h>
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[d8db519] | 38 | #include <errno.h>
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[44a7ee5] | 39 | #include <mem.h>
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[d8db519] | 40 | #include <interrupt.h>
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| 41 | #include <console/console.h>
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| 42 | #include <syscall/syscall.h>
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| 43 | #include <sysinfo/sysinfo.h>
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| 44 | #include <arch/bios/bios.h>
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| 45 | #include <arch/boot/boot.h>
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| 46 | #include <arch/drivers/i8254.h>
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| 47 | #include <arch/syscall.h>
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| 48 | #include <genarch/acpi/acpi.h>
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[f245145] | 49 | #include <genarch/drivers/ega/ega.h>
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[411b6a6] | 50 | #include <genarch/drivers/i8042/i8042.h>
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[87a5796] | 51 | #include <genarch/drivers/i8259/i8259.h>
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[3296df5] | 52 | #include <genarch/drivers/ns16550/ns16550.h>
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[d8db519] | 53 | #include <genarch/drivers/legacy/ia32/io.h>
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| 54 | #include <genarch/fb/bfb.h>
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[411b6a6] | 55 | #include <genarch/kbrd/kbrd.h>
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[3296df5] | 56 | #include <genarch/srln/srln.h>
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[d8db519] | 57 | #include <genarch/multiboot/multiboot.h>
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| 58 | #include <genarch/multiboot/multiboot2.h>
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[1a5eca4] | 59 | #include <arch/pm.h>
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| 60 | #include <arch/vreg.h>
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| 61 | #include <arch/kseg.h>
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[b9e97fb] | 62 |
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[26678e5] | 63 | #ifdef CONFIG_SMP
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| 64 | #include <arch/smp/apic.h>
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| 65 | #endif
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| 66 |
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[36df4109] | 67 | static void amd64_pre_mm_init(void);
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| 68 | static void amd64_post_mm_init(void);
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| 69 | static void amd64_post_cpu_init(void);
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| 70 | static void amd64_pre_smp_init(void);
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| 71 | static void amd64_post_smp_init(void);
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| 72 |
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| 73 | arch_ops_t amd64_ops = {
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| 74 | .pre_mm_init = amd64_pre_mm_init,
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| 75 | .post_mm_init = amd64_post_mm_init,
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| 76 | .post_cpu_init = amd64_post_cpu_init,
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| 77 | .pre_smp_init = amd64_pre_smp_init,
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| 78 | .post_smp_init = amd64_post_smp_init
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| 79 | };
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| 80 |
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| 81 | arch_ops_t *arch_ops = &amd64_ops;
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| 82 |
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[5d8d71e] | 83 | /** Perform amd64-specific initialization before main_bsp() is called.
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| 84 | *
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[1f5c9c96] | 85 | * @param signature Multiboot signature.
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| 86 | * @param info Multiboot information structure.
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| 87 | *
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[5d8d71e] | 88 | */
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[36df4109] | 89 | void amd64_pre_main(uint32_t signature, void *info)
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[5d8d71e] | 90 | {
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| 91 | /* Parse multiboot information obtained from the bootloader. */
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[1f5c9c96] | 92 | multiboot_info_parse(signature, (multiboot_info_t *) info);
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| 93 | multiboot2_info_parse(signature, (multiboot2_info_t *) info);
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[a35b458] | 94 |
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[5d8d71e] | 95 | #ifdef CONFIG_SMP
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[bae43dc] | 96 | size_t unmapped_size = (uintptr_t) unmapped_end - BOOT_OFFSET;
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[5d8d71e] | 97 | /* Copy AP bootstrap routines below 1 MB. */
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[8a1afd2] | 98 | memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET, unmapped_size);
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[5d8d71e] | 99 | #endif
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| 100 | }
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| 101 |
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[36df4109] | 102 | void amd64_pre_mm_init(void)
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[b9e97fb] | 103 | {
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[4fb6bf36] | 104 | /* Enable no-execute pages */
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[811770c] | 105 | write_msr(AMD_MSR_EFER, read_msr(AMD_MSR_EFER) | AMD_NXE);
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[3396f59] | 106 | /* Enable FPU */
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| 107 | cpu_setup_fpu();
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[a35b458] | 108 |
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[49a39c2] | 109 | /* Initialize segmentation */
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[b9e97fb] | 110 | pm_init();
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[a35b458] | 111 |
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[811770c] | 112 | /* Disable I/O on nonprivileged levels, clear the nested-thread flag */
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| 113 | write_rflags(read_rflags() & ~(RFLAGS_IOPL | RFLAGS_NT));
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[49a39c2] | 114 | /* Disable alignment check */
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[811770c] | 115 | write_cr0(read_cr0() & ~CR0_AM);
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[a35b458] | 116 |
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[b9e97fb] | 117 | if (config.cpu_active == 1) {
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[8607db8] | 118 | interrupt_init();
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[b9e97fb] | 119 | bios_init();
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[a35b458] | 120 |
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[8607db8] | 121 | /* PIC */
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[d1cbad5] | 122 | i8259_init((i8259_t *) I8259_PIC0_BASE,
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[a773b8b] | 123 | (i8259_t *) I8259_PIC1_BASE, IRQ_PIC1, IVT_IRQBASE,
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| 124 | IVT_IRQBASE + 8);
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[bbb99f82] | 125 |
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| 126 | /*
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| 127 | * Set the enable/disable IRQs handlers.
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| 128 | * Set the End-of-Interrupt handler.
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| 129 | */
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| 130 | enable_irqs_function = pic_enable_irqs;
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| 131 | disable_irqs_function = pic_disable_irqs;
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| 132 | eoi_function = pic_eoi;
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| 133 | irqs_info = "i8259";
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[b9e97fb] | 134 | }
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| 135 | }
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| 136 |
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[36df4109] | 137 | void amd64_post_mm_init(void)
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[b9e97fb] | 138 | {
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[1a5eca4] | 139 | vreg_init();
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| 140 | kseg_init();
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| 141 |
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[b9e97fb] | 142 | if (config.cpu_active == 1) {
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[8607db8] | 143 | /* Initialize IRQ routing */
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| 144 | irq_init(IRQ_COUNT, IRQ_COUNT);
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[a35b458] | 145 |
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[8607db8] | 146 | /* hard clock */
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| 147 | i8254_init();
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[a35b458] | 148 |
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[a71c158] | 149 | #if (defined(CONFIG_FB) || defined(CONFIG_EGA))
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[1f5c9c96] | 150 | bool bfb = false;
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[a71c158] | 151 | #endif
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[a35b458] | 152 |
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[de07bcf] | 153 | #ifdef CONFIG_FB
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[1f5c9c96] | 154 | bfb = bfb_init();
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[de07bcf] | 155 | #endif
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[a35b458] | 156 |
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[ec944b1] | 157 | #ifdef CONFIG_EGA
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[1f5c9c96] | 158 | if (!bfb) {
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[a71c158] | 159 | outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
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| 160 | if (egadev)
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| 161 | stdout_wire(egadev);
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| 162 | }
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[ec944b1] | 163 | #endif
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[a35b458] | 164 |
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[381465e] | 165 | /* Merge all memory zones to 1 big zone */
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| 166 | zone_merge_all();
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[b9e97fb] | 167 | }
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[a35b458] | 168 |
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[dd4d6b0] | 169 | /* Setup fast SYSCALL/SYSRET */
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| 170 | syscall_setup_cpu();
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[b9e97fb] | 171 | }
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[7df54df] | 172 |
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[36df4109] | 173 | void amd64_post_cpu_init(void)
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[26678e5] | 174 | {
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| 175 | #ifdef CONFIG_SMP
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| 176 | if (config.cpu_active > 1) {
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| 177 | l_apic_init();
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| 178 | l_apic_debug();
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| 179 | }
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| 180 | #endif
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| 181 | }
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| 182 |
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[36df4109] | 183 | void amd64_pre_smp_init(void)
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[7df54df] | 184 | {
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| 185 | if (config.cpu_active == 1) {
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[0b5f9fa] | 186 | #ifdef CONFIG_SMP
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[7df54df] | 187 | acpi_init();
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[0b5f9fa] | 188 | #endif /* CONFIG_SMP */
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[7df54df] | 189 | }
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| 190 | }
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| 191 |
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[36df4109] | 192 | void amd64_post_smp_init(void)
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[7453929] | 193 | {
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[eff1f033] | 194 | /* Currently the only supported platform for amd64 is 'pc'. */
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| 195 | static const char *platform = "pc";
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| 196 |
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| 197 | sysinfo_set_item_data("platform", NULL, (void *) platform,
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| 198 | str_size(platform));
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| 199 |
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[4df7d3a] | 200 | #ifdef CONFIG_PC_KBD
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| 201 | /*
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| 202 | * Initialize the i8042 controller. Then initialize the keyboard
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| 203 | * module and connect it to i8042. Enable keyboard interrupts.
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| 204 | */
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[c2417bc] | 205 | i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
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| 206 | if (i8042_instance) {
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| 207 | kbrd_instance_t *kbrd_instance = kbrd_init();
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| 208 | if (kbrd_instance) {
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| 209 | indev_t *sink = stdin_wire();
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| 210 | indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
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| 211 | i8042_wire(i8042_instance, kbrd);
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| 212 | trap_virtual_enable_irqs(1 << IRQ_KBD);
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[385a3d6] | 213 | trap_virtual_enable_irqs(1 << IRQ_MOUSE);
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[c2417bc] | 214 | }
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[4df7d3a] | 215 | }
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| 216 | #endif
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[3296df5] | 217 |
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[6bbe470] | 218 | #if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
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[3296df5] | 219 | /*
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[6bbe470] | 220 | * Initialize the ns16550 controller.
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[3296df5] | 221 | */
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[21b6307] | 222 | #ifdef CONFIG_NS16550_OUT
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| 223 | outdev_t *ns16550_out;
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| 224 | outdev_t **ns16550_out_ptr = &ns16550_out;
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| 225 | #else
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| 226 | outdev_t **ns16550_out_ptr = NULL;
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| 227 | #endif
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[3bacee1] | 228 | ns16550_instance_t *ns16550_instance =
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| 229 | ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
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[21b6307] | 230 | ns16550_out_ptr);
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[3296df5] | 231 | if (ns16550_instance) {
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[6bbe470] | 232 | #ifdef CONFIG_NS16550
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[3296df5] | 233 | srln_instance_t *srln_instance = srln_init();
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| 234 | if (srln_instance) {
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| 235 | indev_t *sink = stdin_wire();
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| 236 | indev_t *srln = srln_wire(srln_instance, sink);
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| 237 | ns16550_wire(ns16550_instance, srln);
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[5030acad] | 238 | trap_virtual_enable_irqs(1 << IRQ_NS16550);
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[3296df5] | 239 | }
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| 240 | #endif
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[6bbe470] | 241 | #ifdef CONFIG_NS16550_OUT
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| 242 | if (ns16550_out) {
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| 243 | stdout_wire(ns16550_out);
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| 244 | }
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| 245 | #endif
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[24b06199] | 246 | }
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| 247 | #endif
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[a35b458] | 248 |
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[acc7ce4] | 249 | if (irqs_info != NULL)
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| 250 | sysinfo_set_item_val(irqs_info, NULL, true);
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[7453929] | 251 | }
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| 252 |
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[7df54df] | 253 | void calibrate_delay_loop(void)
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| 254 | {
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| 255 | i8254_calibrate_delay_loop();
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[8607db8] | 256 | if (config.cpu_active == 1) {
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| 257 | /*
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| 258 | * This has to be done only on UP.
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| 259 | * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
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| 260 | */
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| 261 | i8254_normal_operation();
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| 262 | }
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[7df54df] | 263 | }
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[281b607] | 264 |
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[6da1013f] | 265 | /** Construct function pointer
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| 266 | *
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| 267 | * @param fptr function pointer structure
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| 268 | * @param addr function address
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| 269 | * @param caller calling function address
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| 270 | *
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| 271 | * @return address of the function pointer
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| 272 | *
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| 273 | */
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| 274 | void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
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| 275 | {
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| 276 | return addr;
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| 277 | }
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| 278 |
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[149d14e5] | 279 | void arch_reboot(void)
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| 280 | {
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| 281 | #ifdef CONFIG_PC_KBD
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| 282 | i8042_cpu_reset((i8042_t *) I8042_BASE);
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| 283 | #endif
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| 284 | }
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| 285 |
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[3a2f8aa] | 286 | void irq_initialize_arch(irq_t *irq)
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| 287 | {
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| 288 | (void) irq;
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| 289 | }
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| 290 |
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[287920f] | 291 | /** @}
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[b45c443] | 292 | */
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