source: mainline/kernel/arch/amd64/src/amd64.c@ 83dab11

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 83dab11 was 83dab11, checked in by Jiri Svoboda <jiri@…>, 8 years ago

Replace usage of typedefs.h with includes of more specific, standard headers, where applicable.

  • Property mode set to 100644
File size: 7.0 KB
RevLine 
[b9e97fb]1/*
[df4ed85]2 * Copyright (c) 2005 Ondrej Palkovsky
[b9e97fb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[287920f]29/** @addtogroup amd64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[b9e97fb]35#include <arch.h>
[36df4109]36#include <arch/arch.h>
[83dab11]37#include <stdint.h>
[d8db519]38#include <errno.h>
[44a7ee5]39#include <mem.h>
[d8db519]40#include <interrupt.h>
41#include <console/console.h>
42#include <syscall/syscall.h>
43#include <sysinfo/sysinfo.h>
44#include <arch/bios/bios.h>
45#include <arch/boot/boot.h>
46#include <arch/drivers/i8254.h>
47#include <arch/drivers/i8259.h>
48#include <arch/syscall.h>
49#include <genarch/acpi/acpi.h>
[f245145]50#include <genarch/drivers/ega/ega.h>
[411b6a6]51#include <genarch/drivers/i8042/i8042.h>
[3296df5]52#include <genarch/drivers/ns16550/ns16550.h>
[d8db519]53#include <genarch/drivers/legacy/ia32/io.h>
54#include <genarch/fb/bfb.h>
[411b6a6]55#include <genarch/kbrd/kbrd.h>
[3296df5]56#include <genarch/srln/srln.h>
[d8db519]57#include <genarch/multiboot/multiboot.h>
58#include <genarch/multiboot/multiboot2.h>
[1a5eca4]59#include <arch/pm.h>
60#include <arch/vreg.h>
61#include <arch/kseg.h>
[b9e97fb]62
[26678e5]63#ifdef CONFIG_SMP
64#include <arch/smp/apic.h>
65#endif
66
[36df4109]67static void amd64_pre_mm_init(void);
68static void amd64_post_mm_init(void);
69static void amd64_post_cpu_init(void);
70static void amd64_pre_smp_init(void);
71static void amd64_post_smp_init(void);
72
73arch_ops_t amd64_ops = {
74 .pre_mm_init = amd64_pre_mm_init,
75 .post_mm_init = amd64_post_mm_init,
76 .post_cpu_init = amd64_post_cpu_init,
77 .pre_smp_init = amd64_pre_smp_init,
78 .post_smp_init = amd64_post_smp_init
79};
80
81arch_ops_t *arch_ops = &amd64_ops;
82
[5d8d71e]83/** Perform amd64-specific initialization before main_bsp() is called.
84 *
[1f5c9c96]85 * @param signature Multiboot signature.
86 * @param info Multiboot information structure.
87 *
[5d8d71e]88 */
[36df4109]89void amd64_pre_main(uint32_t signature, void *info)
[5d8d71e]90{
91 /* Parse multiboot information obtained from the bootloader. */
[1f5c9c96]92 multiboot_info_parse(signature, (multiboot_info_t *) info);
93 multiboot2_info_parse(signature, (multiboot2_info_t *) info);
[5d8d71e]94
95#ifdef CONFIG_SMP
96 /* Copy AP bootstrap routines below 1 MB. */
97 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
98 (size_t) &_hardcoded_unmapped_size);
99#endif
100}
101
[36df4109]102void amd64_pre_mm_init(void)
[b9e97fb]103{
[4fb6bf36]104 /* Enable no-execute pages */
[811770c]105 write_msr(AMD_MSR_EFER, read_msr(AMD_MSR_EFER) | AMD_NXE);
[3396f59]106 /* Enable FPU */
107 cpu_setup_fpu();
[2ddcc7b]108
[49a39c2]109 /* Initialize segmentation */
[b9e97fb]110 pm_init();
[4fb6bf36]111
[811770c]112 /* Disable I/O on nonprivileged levels, clear the nested-thread flag */
113 write_rflags(read_rflags() & ~(RFLAGS_IOPL | RFLAGS_NT));
[49a39c2]114 /* Disable alignment check */
[811770c]115 write_cr0(read_cr0() & ~CR0_AM);
[2ddcc7b]116
[b9e97fb]117 if (config.cpu_active == 1) {
[8607db8]118 interrupt_init();
[b9e97fb]119 bios_init();
[8607db8]120
121 /* PIC */
122 i8259_init();
[b9e97fb]123 }
124}
125
[36df4109]126void amd64_post_mm_init(void)
[b9e97fb]127{
[1a5eca4]128 vreg_init();
129 kseg_init();
130
[b9e97fb]131 if (config.cpu_active == 1) {
[8607db8]132 /* Initialize IRQ routing */
133 irq_init(IRQ_COUNT, IRQ_COUNT);
134
135 /* hard clock */
136 i8254_init();
[ec944b1]137
[a71c158]138#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
[1f5c9c96]139 bool bfb = false;
[a71c158]140#endif
141
[de07bcf]142#ifdef CONFIG_FB
[1f5c9c96]143 bfb = bfb_init();
[de07bcf]144#endif
[a71c158]145
[ec944b1]146#ifdef CONFIG_EGA
[1f5c9c96]147 if (!bfb) {
[a71c158]148 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
149 if (egadev)
150 stdout_wire(egadev);
151 }
[ec944b1]152#endif
[8607db8]153
[381465e]154 /* Merge all memory zones to 1 big zone */
155 zone_merge_all();
[b9e97fb]156 }
[4cc2ddd]157
[dd4d6b0]158 /* Setup fast SYSCALL/SYSRET */
159 syscall_setup_cpu();
[b9e97fb]160}
[7df54df]161
[36df4109]162void amd64_post_cpu_init(void)
[26678e5]163{
164#ifdef CONFIG_SMP
165 if (config.cpu_active > 1) {
166 l_apic_init();
167 l_apic_debug();
168 }
169#endif
170}
171
[36df4109]172void amd64_pre_smp_init(void)
[7df54df]173{
174 if (config.cpu_active == 1) {
[0b5f9fa]175#ifdef CONFIG_SMP
[7df54df]176 acpi_init();
[0b5f9fa]177#endif /* CONFIG_SMP */
[7df54df]178 }
179}
180
[36df4109]181void amd64_post_smp_init(void)
[7453929]182{
[eff1f033]183 /* Currently the only supported platform for amd64 is 'pc'. */
184 static const char *platform = "pc";
185
186 sysinfo_set_item_data("platform", NULL, (void *) platform,
187 str_size(platform));
188
[4df7d3a]189#ifdef CONFIG_PC_KBD
190 /*
191 * Initialize the i8042 controller. Then initialize the keyboard
192 * module and connect it to i8042. Enable keyboard interrupts.
193 */
[c2417bc]194 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
195 if (i8042_instance) {
196 kbrd_instance_t *kbrd_instance = kbrd_init();
197 if (kbrd_instance) {
198 indev_t *sink = stdin_wire();
199 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
200 i8042_wire(i8042_instance, kbrd);
201 trap_virtual_enable_irqs(1 << IRQ_KBD);
[385a3d6]202 trap_virtual_enable_irqs(1 << IRQ_MOUSE);
[c2417bc]203 }
[4df7d3a]204 }
205#endif
[3296df5]206
[6bbe470]207#if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
[3296df5]208 /*
[6bbe470]209 * Initialize the ns16550 controller.
[3296df5]210 */
[21b6307]211#ifdef CONFIG_NS16550_OUT
212 outdev_t *ns16550_out;
213 outdev_t **ns16550_out_ptr = &ns16550_out;
214#else
215 outdev_t **ns16550_out_ptr = NULL;
216#endif
[3296df5]217 ns16550_instance_t *ns16550_instance
[21b6307]218 = ns16550_init((ns16550_t *) NS16550_BASE, IRQ_NS16550, NULL, NULL,
219 ns16550_out_ptr);
[3296df5]220 if (ns16550_instance) {
[6bbe470]221#ifdef CONFIG_NS16550
[3296df5]222 srln_instance_t *srln_instance = srln_init();
223 if (srln_instance) {
224 indev_t *sink = stdin_wire();
225 indev_t *srln = srln_wire(srln_instance, sink);
226 ns16550_wire(ns16550_instance, srln);
[5030acad]227 trap_virtual_enable_irqs(1 << IRQ_NS16550);
[3296df5]228 }
229#endif
[6bbe470]230#ifdef CONFIG_NS16550_OUT
231 if (ns16550_out) {
232 stdout_wire(ns16550_out);
233 }
234#endif
[24b06199]235 }
236#endif
[849ed54]237
[acc7ce4]238 if (irqs_info != NULL)
239 sysinfo_set_item_val(irqs_info, NULL, true);
[7453929]240}
241
[7df54df]242void calibrate_delay_loop(void)
243{
244 i8254_calibrate_delay_loop();
[8607db8]245 if (config.cpu_active == 1) {
246 /*
247 * This has to be done only on UP.
248 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
249 */
250 i8254_normal_operation();
251 }
[7df54df]252}
[281b607]253
[6da1013f]254/** Construct function pointer
255 *
256 * @param fptr function pointer structure
257 * @param addr function address
258 * @param caller calling function address
259 *
260 * @return address of the function pointer
261 *
262 */
263void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
264{
265 return addr;
266}
267
[149d14e5]268void arch_reboot(void)
269{
270#ifdef CONFIG_PC_KBD
271 i8042_cpu_reset((i8042_t *) I8042_BASE);
272#endif
273}
274
[3a2f8aa]275void irq_initialize_arch(irq_t *irq)
276{
277 (void) irq;
278}
279
[287920f]280/** @}
[b45c443]281 */
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