source: mainline/kernel/arch/amd64/include/mm/page.h@ 1ba41c5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 1ba41c5 was df4ed85, checked in by Jakub Jermar <jakub@…>, 19 years ago

© versus ©

  • Property mode set to 100644
File size: 7.2 KB
Line 
1/*
2 * Copyright (c) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64mm
30 * @{
31 */
32/** @file
33 */
34
35/** Paging on AMD64
36 *
37 * The space is divided in positive numbers - userspace and
38 * negative numbers - kernel space. The 'negative' space starting
39 * with 0xffff800000000000 and ending with 0xffffffff80000000
40 * (-2GB) is identically mapped physical memory. The area
41 * (0xffffffff80000000 ... 0xffffffffffffffff is again identically
42 * mapped first 2GB.
43 *
44 * ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel
45 */
46
47#ifndef KERN_amd64_PAGE_H_
48#define KERN_amd64_PAGE_H_
49
50#include <arch/mm/frame.h>
51
52#define PAGE_WIDTH FRAME_WIDTH
53#define PAGE_SIZE FRAME_SIZE
54
55#define PAGE_COLOR_BITS 0 /* dummy */
56
57#ifdef KERNEL
58
59#ifndef __ASM__
60# include <mm/page.h>
61# include <arch/types.h>
62#endif
63
64#ifndef __ASM__
65static inline uintptr_t ka2pa(uintptr_t x)
66{
67 if (x > 0xffffffff80000000)
68 return x - 0xffffffff80000000;
69 else
70 return x - 0xffff800000000000;
71}
72# define KA2PA(x) ka2pa((uintptr_t)x)
73# define PA2KA_CODE(x) (((uintptr_t) (x)) + 0xffffffff80000000)
74# define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000)
75#else
76# define KA2PA(x) ((x) - 0xffffffff80000000)
77# define PA2KA(x) ((x) + 0xffffffff80000000)
78#endif
79
80#define PTL0_ENTRIES_ARCH 512
81#define PTL1_ENTRIES_ARCH 512
82#define PTL2_ENTRIES_ARCH 512
83#define PTL3_ENTRIES_ARCH 512
84
85#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>39)&0x1ff)
86#define PTL1_INDEX_ARCH(vaddr) (((vaddr)>>30)&0x1ff)
87#define PTL2_INDEX_ARCH(vaddr) (((vaddr)>>21)&0x1ff)
88#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0x1ff)
89
90#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
91#define GET_PTL2_ADDRESS_ARCH(ptl1, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))
92#define GET_PTL3_ADDRESS_ARCH(ptl2, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 )))
93#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t *) ((((uint64_t) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 )))
94
95#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((uintptr_t) (ptl0)))
96#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) set_pt_addr((pte_t *)(ptl0), (index_t)(i), a)
97#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) set_pt_addr((pte_t *)(ptl1), (index_t)(i), a)
98#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) set_pt_addr((pte_t *)(ptl2), (index_t)(i), a)
99#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) set_pt_addr((pte_t *)(ptl3), (index_t)(i), a)
100
101#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
102#define GET_PTL2_FLAGS_ARCH(ptl1, i) get_pt_flags((pte_t *)(ptl1), (index_t)(i))
103#define GET_PTL3_FLAGS_ARCH(ptl2, i) get_pt_flags((pte_t *)(ptl2), (index_t)(i))
104#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i))
105
106#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
107#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) set_pt_flags((pte_t *)(ptl1), (index_t)(i), (x))
108#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) set_pt_flags((pte_t *)(ptl2), (index_t)(i), (x))
109#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
110
111#define PTE_VALID_ARCH(p) (*((uint64_t *) (p)) != 0)
112#define PTE_PRESENT_ARCH(p) ((p)->present != 0)
113#define PTE_GET_FRAME_ARCH(p) ((((uintptr_t)(p)->addr_12_31)<<12) | ((uintptr_t)(p)->addr_32_51<<32))
114#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0)
115#define PTE_EXECUTABLE_ARCH(p) ((p)->no_execute == 0)
116
117#ifndef __ASM__
118
119/* Page fault error codes. */
120
121/** When bit on this position is 0, the page fault was caused by a not-present page. */
122#define PFERR_CODE_P (1<<0)
123
124/** When bit on this position is 1, the page fault was caused by a write. */
125#define PFERR_CODE_RW (1<<1)
126
127/** When bit on this position is 1, the page fault was caused in user mode. */
128#define PFERR_CODE_US (1<<2)
129
130/** When bit on this position is 1, a reserved bit was set in page directory. */
131#define PFERR_CODE_RSVD (1<<3)
132
133/** When bit on this position os 1, the page fault was caused during instruction fecth. */
134#define PFERR_CODE_ID (1<<4)
135
136/** Page Table Entry. */
137struct page_specifier {
138 unsigned present : 1;
139 unsigned writeable : 1;
140 unsigned uaccessible : 1;
141 unsigned page_write_through : 1;
142 unsigned page_cache_disable : 1;
143 unsigned accessed : 1;
144 unsigned dirty : 1;
145 unsigned unused: 1;
146 unsigned global : 1;
147 unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */
148 unsigned avl : 2;
149 unsigned addr_12_31 : 30;
150 unsigned addr_32_51 : 21;
151 unsigned no_execute : 1;
152} __attribute__ ((packed));
153
154static inline int get_pt_flags(pte_t *pt, index_t i)
155{
156 pte_t *p = &pt[i];
157
158 return (
159 (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
160 (!p->present)<<PAGE_PRESENT_SHIFT |
161 p->uaccessible<<PAGE_USER_SHIFT |
162 1<<PAGE_READ_SHIFT |
163 p->writeable<<PAGE_WRITE_SHIFT |
164 (!p->no_execute)<<PAGE_EXEC_SHIFT |
165 p->global<<PAGE_GLOBAL_SHIFT
166 );
167}
168
169static inline void set_pt_addr(pte_t *pt, index_t i, uintptr_t a)
170{
171 pte_t *p = &pt[i];
172
173 p->addr_12_31 = (a >> 12) & 0xfffff;
174 p->addr_32_51 = a >> 32;
175}
176
177static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
178{
179 pte_t *p = &pt[i];
180
181 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
182 p->present = !(flags & PAGE_NOT_PRESENT);
183 p->uaccessible = (flags & PAGE_USER) != 0;
184 p->writeable = (flags & PAGE_WRITE) != 0;
185 p->no_execute = (flags & PAGE_EXEC) == 0;
186 p->global = (flags & PAGE_GLOBAL) != 0;
187
188 /*
189 * Ensure that there is at least one bit set even if the present bit is cleared.
190 */
191 p->soft_valid = 1;
192}
193
194extern void page_arch_init(void);
195extern void page_fault(int n, istate_t *istate);
196
197#endif /* __ASM__ */
198
199#endif /* KERNEL */
200
201#endif
202
203/** @}
204 */
Note: See TracBrowser for help on using the repository browser.