source: mainline/kernel/arch/amd64/include/mm/page.h@ 11675207

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 11675207 was 11675207, checked in by jermar <jermar@…>, 17 years ago

Move everything to kernel/.

  • Property mode set to 100644
File size: 7.1 KB
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1/*
2 * Copyright (C) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64mm
30 * @{
31 */
32/** @file
33 */
34
35/** Paging on AMD64
36 *
37 * The space is divided in positive numbers - userspace and
38 * negative numbers - kernel space. The 'negative' space starting
39 * with 0xffff800000000000 and ending with 0xffffffff80000000
40 * (-2GB) is identically mapped physical memory. The area
41 * (0xffffffff80000000 ... 0xffffffffffffffff is again identically
42 * mapped first 2GB.
43 *
44 * ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel
45 */
46
47#ifndef __amd64_PAGE_H__
48#define __amd64_PAGE_H__
49
50#include <arch/mm/frame.h>
51
52#define PAGE_WIDTH FRAME_WIDTH
53#define PAGE_SIZE FRAME_SIZE
54
55#ifdef KERNEL
56
57#ifndef __ASM__
58# include <mm/page.h>
59# include <arch/types.h>
60#endif
61
62#ifndef __ASM__
63static inline uintptr_t ka2pa(uintptr_t x)
64{
65 if (x > 0xffffffff80000000)
66 return x - 0xffffffff80000000;
67 else
68 return x - 0xffff800000000000;
69}
70# define KA2PA(x) ka2pa((uintptr_t)x)
71# define PA2KA_CODE(x) (((uintptr_t) (x)) + 0xffffffff80000000)
72# define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000)
73#else
74# define KA2PA(x) ((x) - 0xffffffff80000000)
75# define PA2KA(x) ((x) + 0xffffffff80000000)
76#endif
77
78#define PTL0_ENTRIES_ARCH 512
79#define PTL1_ENTRIES_ARCH 512
80#define PTL2_ENTRIES_ARCH 512
81#define PTL3_ENTRIES_ARCH 512
82
83#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>39)&0x1ff)
84#define PTL1_INDEX_ARCH(vaddr) (((vaddr)>>30)&0x1ff)
85#define PTL2_INDEX_ARCH(vaddr) (((vaddr)>>21)&0x1ff)
86#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0x1ff)
87
88#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
89#define GET_PTL2_ADDRESS_ARCH(ptl1, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))
90#define GET_PTL3_ADDRESS_ARCH(ptl2, i) ((pte_t *) ((((uint64_t) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 )))
91#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t *) ((((uint64_t) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((uint64_t) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 )))
92
93#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((uintptr_t) (ptl0)))
94#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) set_pt_addr((pte_t *)(ptl0), (index_t)(i), a)
95#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) set_pt_addr((pte_t *)(ptl1), (index_t)(i), a)
96#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) set_pt_addr((pte_t *)(ptl2), (index_t)(i), a)
97#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) set_pt_addr((pte_t *)(ptl3), (index_t)(i), a)
98
99#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
100#define GET_PTL2_FLAGS_ARCH(ptl1, i) get_pt_flags((pte_t *)(ptl1), (index_t)(i))
101#define GET_PTL3_FLAGS_ARCH(ptl2, i) get_pt_flags((pte_t *)(ptl2), (index_t)(i))
102#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i))
103
104#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
105#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) set_pt_flags((pte_t *)(ptl1), (index_t)(i), (x))
106#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) set_pt_flags((pte_t *)(ptl2), (index_t)(i), (x))
107#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
108
109#define PTE_VALID_ARCH(p) (*((uint64_t *) (p)) != 0)
110#define PTE_PRESENT_ARCH(p) ((p)->present != 0)
111#define PTE_GET_FRAME_ARCH(p) ((((uintptr_t)(p)->addr_12_31)<<12) | ((uintptr_t)(p)->addr_32_51<<32))
112#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0)
113#define PTE_EXECUTABLE_ARCH(p) ((p)->no_execute == 0)
114
115#ifndef __ASM__
116
117/* Page fault error codes. */
118
119/** When bit on this position is 0, the page fault was caused by a not-present page. */
120#define PFERR_CODE_P (1<<0)
121
122/** When bit on this position is 1, the page fault was caused by a write. */
123#define PFERR_CODE_RW (1<<1)
124
125/** When bit on this position is 1, the page fault was caused in user mode. */
126#define PFERR_CODE_US (1<<2)
127
128/** When bit on this position is 1, a reserved bit was set in page directory. */
129#define PFERR_CODE_RSVD (1<<3)
130
131/** When bit on this position os 1, the page fault was caused during instruction fecth. */
132#define PFERR_CODE_ID (1<<4)
133
134/** Page Table Entry. */
135struct page_specifier {
136 unsigned present : 1;
137 unsigned writeable : 1;
138 unsigned uaccessible : 1;
139 unsigned page_write_through : 1;
140 unsigned page_cache_disable : 1;
141 unsigned accessed : 1;
142 unsigned dirty : 1;
143 unsigned unused: 1;
144 unsigned global : 1;
145 unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */
146 unsigned avl : 2;
147 unsigned addr_12_31 : 30;
148 unsigned addr_32_51 : 21;
149 unsigned no_execute : 1;
150} __attribute__ ((packed));
151
152static inline int get_pt_flags(pte_t *pt, index_t i)
153{
154 pte_t *p = &pt[i];
155
156 return (
157 (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
158 (!p->present)<<PAGE_PRESENT_SHIFT |
159 p->uaccessible<<PAGE_USER_SHIFT |
160 1<<PAGE_READ_SHIFT |
161 p->writeable<<PAGE_WRITE_SHIFT |
162 (!p->no_execute)<<PAGE_EXEC_SHIFT |
163 p->global<<PAGE_GLOBAL_SHIFT
164 );
165}
166
167static inline void set_pt_addr(pte_t *pt, index_t i, uintptr_t a)
168{
169 pte_t *p = &pt[i];
170
171 p->addr_12_31 = (a >> 12) & 0xfffff;
172 p->addr_32_51 = a >> 32;
173}
174
175static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
176{
177 pte_t *p = &pt[i];
178
179 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
180 p->present = !(flags & PAGE_NOT_PRESENT);
181 p->uaccessible = (flags & PAGE_USER) != 0;
182 p->writeable = (flags & PAGE_WRITE) != 0;
183 p->no_execute = (flags & PAGE_EXEC) == 0;
184 p->global = (flags & PAGE_GLOBAL) != 0;
185
186 /*
187 * Ensure that there is at least one bit set even if the present bit is cleared.
188 */
189 p->soft_valid = 1;
190}
191
192extern void page_arch_init(void);
193
194#endif /* __ASM__ */
195
196#endif /* KERNEL */
197
198#endif
199
200/** @}
201 */
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