source: mainline/kernel/arch/amd64/include/cpu.h@ da581872

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since da581872 was e13daa5d, checked in by Jakub Jermar <jakub@…>, 17 years ago

Fortify ia32 and amd64 kernels against mallicious uspace applications that set
DF prior to entering the kernel. For AMD64 syscalls, we don't use the CLD
instruction, but make use of the SFMASK MSR instead. Simics works fine with
it, but QEMU seems to have a problem.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_amd64_CPU_H_
36#define KERN_amd64_CPU_H_
37
38#define RFLAGS_IF (1 << 9)
39#define RFLAGS_DF (1 << 10)
40#define RFLAGS_RF (1 << 16)
41
42#define EFER_MSR_NUM 0xc0000080
43#define AMD_SCE_FLAG 0
44#define AMD_LME_FLAG 8
45#define AMD_LMA_FLAG 10
46#define AMD_FFXSR_FLAG 14
47#define AMD_NXE_FLAG 11
48
49/* MSR registers */
50#define AMD_MSR_STAR 0xc0000081
51#define AMD_MSR_LSTAR 0xc0000082
52#define AMD_MSR_SFMASK 0xc0000084
53#define AMD_MSR_FS 0xc0000100
54#define AMD_MSR_GS 0xc0000101
55
56#ifndef __ASM__
57
58#include <arch/pm.h>
59
60typedef struct {
61 int vendor;
62 int family;
63 int model;
64 int stepping;
65 struct tss *tss;
66
67 count_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
68} cpu_arch_t;
69
70struct star_msr {
71
72};
73
74struct lstar_msr {
75
76};
77
78extern void set_efer_flag(int flag);
79extern uint64_t read_efer_flag(void);
80void cpu_setup_fpu(void);
81
82#endif /* __ASM__ */
83
84#endif
85
86/** @}
87 */
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