source: mainline/kernel/arch/amd64/include/cpu.h@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was 586cd56, checked in by Jakub Jermar <jakub@…>, 16 years ago

Use the RFLAGS defines instead of magic numbers.

  • Property mode set to 100644
File size: 2.6 KB
RevLine 
[1141c1a]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[1141c1a]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[1bb2e7a]29/** @addtogroup amd64
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_amd64_CPU_H_
36#define KERN_amd64_CPU_H_
[1141c1a]37
[586cd56]38#define RFLAGS_CF (1 << 0)
39#define RFLAGS_PF (1 << 2)
40#define RFLAGS_AF (1 << 4)
41#define RFLAGS_ZF (1 << 6)
42#define RFLAGS_SF (1 << 7)
43#define RFLAGS_TF (1 << 8)
44#define RFLAGS_IF (1 << 9)
45#define RFLAGS_DF (1 << 10)
46#define RFLAGS_OF (1 << 11)
47#define RFLAGS_RF (1 << 16)
[89344d85]48
49#define EFER_MSR_NUM 0xc0000080
50#define AMD_SCE_FLAG 0
51#define AMD_LME_FLAG 8
52#define AMD_LMA_FLAG 10
53#define AMD_FFXSR_FLAG 14
54#define AMD_NXE_FLAG 11
55
[dd4d6b0]56/* MSR registers */
57#define AMD_MSR_STAR 0xc0000081
58#define AMD_MSR_LSTAR 0xc0000082
59#define AMD_MSR_SFMASK 0xc0000084
[281b607]60#define AMD_MSR_FS 0xc0000100
[37b451f7]61#define AMD_MSR_GS 0xc0000101
[dd4d6b0]62
[89344d85]63#ifndef __ASM__
64
[1141c1a]65#include <arch/pm.h>
66
[f429331]67typedef struct {
[1141c1a]68 int vendor;
69 int family;
70 int model;
71 int stepping;
[99d6fd0]72 tss_t *tss;
[2382d09]73
[98000fb]74 size_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
[f429331]75} cpu_arch_t;
[1141c1a]76
[49a39c2]77struct star_msr {
78};
79
80struct lstar_msr {
81};
[1141c1a]82
[89344d85]83extern void set_efer_flag(int flag);
[7f1c620]84extern uint64_t read_efer_flag(void);
[3396f59]85void cpu_setup_fpu(void);
[89344d85]86
87#endif /* __ASM__ */
[1141c1a]88
89#endif
[b45c443]90
[1bb2e7a]91/** @}
[b45c443]92 */
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