source: mainline/kernel/arch/amd64/include/asm.h@ a522999

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since a522999 was c22531fc, checked in by Martin Decky <martin@…>, 14 years ago

cstyle
(no change in functionality)
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_amd64_ASM_H_
36#define KERN_amd64_ASM_H_
37
38#include <config.h>
39#include <typedefs.h>
40#include <arch/cpu.h>
41#include <trace.h>
42
43#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
44
45/** Return base address of current stack.
46 *
47 * Return the base address of the current stack.
48 * The stack is assumed to be STACK_SIZE bytes long.
49 * The stack must start on page boundary.
50 *
51 */
52NO_TRACE static inline uintptr_t get_stack_base(void)
53{
54 uintptr_t v;
55
56 asm volatile (
57 "andq %%rsp, %[v]\n"
58 : [v] "=r" (v)
59 : "0" (~((uint64_t) STACK_SIZE - 1))
60 );
61
62 return v;
63}
64
65NO_TRACE static inline void cpu_sleep(void)
66{
67 asm volatile (
68 "hlt\n"
69 );
70}
71
72NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
73{
74 while (true) {
75 asm volatile (
76 "hlt\n"
77 );
78 }
79}
80
81/** Byte from port
82 *
83 * Get byte from port
84 *
85 * @param port Port to read from
86 * @return Value read
87 *
88 */
89NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
90{
91 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
92 uint8_t val;
93
94 asm volatile (
95 "inb %w[port], %b[val]\n"
96 : [val] "=a" (val)
97 : [port] "d" (port)
98 );
99
100 return val;
101 } else
102 return (uint8_t) *port;
103}
104
105/** Word from port
106 *
107 * Get word from port
108 *
109 * @param port Port to read from
110 * @return Value read
111 *
112 */
113NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
114{
115 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
116 uint16_t val;
117
118 asm volatile (
119 "inw %w[port], %w[val]\n"
120 : [val] "=a" (val)
121 : [port] "d" (port)
122 );
123
124 return val;
125 } else
126 return (uint16_t) *port;
127}
128
129/** Double word from port
130 *
131 * Get double word from port
132 *
133 * @param port Port to read from
134 * @return Value read
135 *
136 */
137NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
138{
139 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
140 uint32_t val;
141
142 asm volatile (
143 "inl %w[port], %[val]\n"
144 : [val] "=a" (val)
145 : [port] "d" (port)
146 );
147
148 return val;
149 } else
150 return (uint32_t) *port;
151}
152
153/** Byte to port
154 *
155 * Output byte to port
156 *
157 * @param port Port to write to
158 * @param val Value to write
159 *
160 */
161NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
162{
163 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
164 asm volatile (
165 "outb %b[val], %w[port]\n"
166 :: [val] "a" (val), [port] "d" (port)
167 );
168 } else
169 *port = val;
170}
171
172/** Word to port
173 *
174 * Output word to port
175 *
176 * @param port Port to write to
177 * @param val Value to write
178 *
179 */
180NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
181{
182 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
183 asm volatile (
184 "outw %w[val], %w[port]\n"
185 :: [val] "a" (val), [port] "d" (port)
186 );
187 } else
188 *port = val;
189}
190
191/** Double word to port
192 *
193 * Output double word to port
194 *
195 * @param port Port to write to
196 * @param val Value to write
197 *
198 */
199NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
200{
201 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
202 asm volatile (
203 "outl %[val], %w[port]\n"
204 :: [val] "a" (val), [port] "d" (port)
205 );
206 } else
207 *port = val;
208}
209
210/** Swap Hidden part of GS register with visible one */
211NO_TRACE static inline void swapgs(void)
212{
213 asm volatile (
214 "swapgs"
215 );
216}
217
218/** Enable interrupts.
219 *
220 * Enable interrupts and return previous
221 * value of EFLAGS.
222 *
223 * @return Old interrupt priority level.
224 *
225 */
226NO_TRACE static inline ipl_t interrupts_enable(void) {
227 ipl_t v;
228
229 asm volatile (
230 "pushfq\n"
231 "popq %[v]\n"
232 "sti\n"
233 : [v] "=r" (v)
234 );
235
236 return v;
237}
238
239/** Disable interrupts.
240 *
241 * Disable interrupts and return previous
242 * value of EFLAGS.
243 *
244 * @return Old interrupt priority level.
245 *
246 */
247NO_TRACE static inline ipl_t interrupts_disable(void) {
248 ipl_t v;
249
250 asm volatile (
251 "pushfq\n"
252 "popq %[v]\n"
253 "cli\n"
254 : [v] "=r" (v)
255 );
256
257 return v;
258}
259
260/** Restore interrupt priority level.
261 *
262 * Restore EFLAGS.
263 *
264 * @param ipl Saved interrupt priority level.
265 *
266 */
267NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
268 asm volatile (
269 "pushq %[ipl]\n"
270 "popfq\n"
271 :: [ipl] "r" (ipl)
272 );
273}
274
275/** Return interrupt priority level.
276 *
277 * Return EFLAFS.
278 *
279 * @return Current interrupt priority level.
280 *
281 */
282NO_TRACE static inline ipl_t interrupts_read(void) {
283 ipl_t v;
284
285 asm volatile (
286 "pushfq\n"
287 "popq %[v]\n"
288 : [v] "=r" (v)
289 );
290
291 return v;
292}
293
294/** Check interrupts state.
295 *
296 * @return True if interrupts are disabled.
297 *
298 */
299NO_TRACE static inline bool interrupts_disabled(void)
300{
301 ipl_t v;
302
303 asm volatile (
304 "pushfq\n"
305 "popq %[v]\n"
306 : [v] "=r" (v)
307 );
308
309 return ((v & RFLAGS_IF) == 0);
310}
311
312/** Write to MSR */
313NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
314{
315 asm volatile (
316 "wrmsr\n"
317 :: "c" (msr),
318 "a" ((uint32_t) (value)),
319 "d" ((uint32_t) (value >> 32))
320 );
321}
322
323NO_TRACE static inline sysarg_t read_msr(uint32_t msr)
324{
325 uint32_t ax, dx;
326
327 asm volatile (
328 "rdmsr\n"
329 : "=a" (ax), "=d" (dx)
330 : "c" (msr)
331 );
332
333 return ((uint64_t) dx << 32) | ax;
334}
335
336/** Enable local APIC
337 *
338 * Enable local APIC in MSR.
339 *
340 */
341NO_TRACE static inline void enable_l_apic_in_msr()
342{
343 asm volatile (
344 "movl $0x1b, %%ecx\n"
345 "rdmsr\n"
346 "orl $(1 << 11),%%eax\n"
347 "orl $(0xfee00000),%%eax\n"
348 "wrmsr\n"
349 ::: "%eax", "%ecx", "%edx"
350 );
351}
352
353/** Invalidate TLB Entry.
354 *
355 * @param addr Address on a page whose TLB entry is to be invalidated.
356 *
357 */
358NO_TRACE static inline void invlpg(uintptr_t addr)
359{
360 asm volatile (
361 "invlpg %[addr]\n"
362 :: [addr] "m" (*((sysarg_t *) addr))
363 );
364}
365
366/** Load GDTR register from memory.
367 *
368 * @param gdtr_reg Address of memory from where to load GDTR.
369 *
370 */
371NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
372{
373 asm volatile (
374 "lgdtq %[gdtr_reg]\n"
375 :: [gdtr_reg] "m" (*gdtr_reg)
376 );
377}
378
379/** Store GDTR register to memory.
380 *
381 * @param gdtr_reg Address of memory to where to load GDTR.
382 *
383 */
384NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
385{
386 asm volatile (
387 "sgdtq %[gdtr_reg]\n"
388 :: [gdtr_reg] "m" (*gdtr_reg)
389 );
390}
391
392/** Load IDTR register from memory.
393 *
394 * @param idtr_reg Address of memory from where to load IDTR.
395 *
396 */
397NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
398{
399 asm volatile (
400 "lidtq %[idtr_reg]\n"
401 :: [idtr_reg] "m" (*idtr_reg));
402}
403
404/** Load TR from descriptor table.
405 *
406 * @param sel Selector specifying descriptor of TSS segment.
407 *
408 */
409NO_TRACE static inline void tr_load(uint16_t sel)
410{
411 asm volatile (
412 "ltr %[sel]"
413 :: [sel] "r" (sel)
414 );
415}
416
417#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
418 { \
419 sysarg_t res; \
420 asm volatile ( \
421 "movq %%" #reg ", %[res]" \
422 : [res] "=r" (res) \
423 ); \
424 return res; \
425 }
426
427#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
428 { \
429 asm volatile ( \
430 "movq %[regn], %%" #reg \
431 :: [regn] "r" (regn) \
432 ); \
433 }
434
435GEN_READ_REG(cr0)
436GEN_READ_REG(cr2)
437GEN_READ_REG(cr3)
438GEN_WRITE_REG(cr3)
439
440GEN_READ_REG(dr0)
441GEN_READ_REG(dr1)
442GEN_READ_REG(dr2)
443GEN_READ_REG(dr3)
444GEN_READ_REG(dr6)
445GEN_READ_REG(dr7)
446
447GEN_WRITE_REG(dr0)
448GEN_WRITE_REG(dr1)
449GEN_WRITE_REG(dr2)
450GEN_WRITE_REG(dr3)
451GEN_WRITE_REG(dr6)
452GEN_WRITE_REG(dr7)
453
454extern void asm_delay_loop(uint32_t);
455extern void asm_fake_loop(uint32_t);
456
457extern uintptr_t int_0;
458extern uintptr_t int_1;
459extern uintptr_t int_2;
460extern uintptr_t int_3;
461extern uintptr_t int_4;
462extern uintptr_t int_5;
463extern uintptr_t int_6;
464extern uintptr_t int_7;
465extern uintptr_t int_8;
466extern uintptr_t int_9;
467extern uintptr_t int_10;
468extern uintptr_t int_11;
469extern uintptr_t int_12;
470extern uintptr_t int_13;
471extern uintptr_t int_14;
472extern uintptr_t int_15;
473extern uintptr_t int_16;
474extern uintptr_t int_17;
475extern uintptr_t int_18;
476extern uintptr_t int_19;
477extern uintptr_t int_20;
478extern uintptr_t int_21;
479extern uintptr_t int_22;
480extern uintptr_t int_23;
481extern uintptr_t int_24;
482extern uintptr_t int_25;
483extern uintptr_t int_26;
484extern uintptr_t int_27;
485extern uintptr_t int_28;
486extern uintptr_t int_29;
487extern uintptr_t int_30;
488extern uintptr_t int_31;
489extern uintptr_t int_32;
490extern uintptr_t int_33;
491extern uintptr_t int_34;
492extern uintptr_t int_35;
493extern uintptr_t int_36;
494extern uintptr_t int_37;
495extern uintptr_t int_38;
496extern uintptr_t int_39;
497extern uintptr_t int_40;
498extern uintptr_t int_41;
499extern uintptr_t int_42;
500extern uintptr_t int_43;
501extern uintptr_t int_44;
502extern uintptr_t int_45;
503extern uintptr_t int_46;
504extern uintptr_t int_47;
505extern uintptr_t int_48;
506extern uintptr_t int_49;
507extern uintptr_t int_50;
508extern uintptr_t int_51;
509extern uintptr_t int_52;
510extern uintptr_t int_53;
511extern uintptr_t int_54;
512extern uintptr_t int_55;
513extern uintptr_t int_56;
514extern uintptr_t int_57;
515extern uintptr_t int_58;
516extern uintptr_t int_59;
517extern uintptr_t int_60;
518extern uintptr_t int_61;
519extern uintptr_t int_62;
520extern uintptr_t int_63;
521
522#endif
523
524/** @}
525 */
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