source: mainline/kernel/arch/amd64/include/arch/asm.h@ 2b264c4

ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2b264c4 was 2b264c4, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 3 years ago

Add architecture-specific spinlock optimization
  • Property mode set to 100644
File size: 9.7 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_amd64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_amd64_ASM_H_
36#define KERN_amd64_ASM_H_
37
38#include <config.h>
39#include <typedefs.h>
40#include <arch/cpu.h>
41#include <trace.h>
42
43#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
44
45_NO_TRACE static inline void cpu_sleep(void)
46{
47 asm volatile (
48 "hlt\n"
49 );
50}
51
52_NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
53{
54 while (true) {
55 asm volatile (
56 "hlt\n"
57 );
58 }
59}
60
61#define ARCH_SPIN_HINT() asm volatile ("pause\n")
62
63/** Byte from port
64 *
65 * Get byte from port
66 *
67 * @param port Port to read from
68 * @return Value read
69 *
70 */
71_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
72{
73 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
74 uint8_t val;
75
76 asm volatile (
77 "inb %w[port], %b[val]\n"
78 : [val] "=a" (val)
79 : [port] "d" (port)
80 );
81
82 return val;
83 } else
84 return (uint8_t) *port;
85}
86
87/** Word from port
88 *
89 * Get word from port
90 *
91 * @param port Port to read from
92 * @return Value read
93 *
94 */
95_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
96{
97 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
98 uint16_t val;
99
100 asm volatile (
101 "inw %w[port], %w[val]\n"
102 : [val] "=a" (val)
103 : [port] "d" (port)
104 );
105
106 return val;
107 } else
108 return (uint16_t) *port;
109}
110
111/** Double word from port
112 *
113 * Get double word from port
114 *
115 * @param port Port to read from
116 * @return Value read
117 *
118 */
119_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
120{
121 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
122 uint32_t val;
123
124 asm volatile (
125 "inl %w[port], %[val]\n"
126 : [val] "=a" (val)
127 : [port] "d" (port)
128 );
129
130 return val;
131 } else
132 return (uint32_t) *port;
133}
134
135/** Byte to port
136 *
137 * Output byte to port
138 *
139 * @param port Port to write to
140 * @param val Value to write
141 *
142 */
143_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
144{
145 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
146 asm volatile (
147 "outb %b[val], %w[port]\n"
148 :: [val] "a" (val), [port] "d" (port)
149 );
150 } else
151 *port = val;
152}
153
154/** Word to port
155 *
156 * Output word to port
157 *
158 * @param port Port to write to
159 * @param val Value to write
160 *
161 */
162_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
163{
164 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
165 asm volatile (
166 "outw %w[val], %w[port]\n"
167 :: [val] "a" (val), [port] "d" (port)
168 );
169 } else
170 *port = val;
171}
172
173/** Double word to port
174 *
175 * Output double word to port
176 *
177 * @param port Port to write to
178 * @param val Value to write
179 *
180 */
181_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
182{
183 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
184 asm volatile (
185 "outl %[val], %w[port]\n"
186 :: [val] "a" (val), [port] "d" (port)
187 );
188 } else
189 *port = val;
190}
191
192_NO_TRACE static inline uint64_t read_rflags(void)
193{
194 uint64_t rflags;
195
196 asm volatile (
197 "pushfq\n"
198 "popq %[v]\n"
199 : [v] "=r" (rflags)
200 );
201
202 return rflags;
203}
204
205_NO_TRACE static inline void write_rflags(uint64_t rflags)
206{
207 asm volatile (
208 "pushq %[v]\n"
209 "popfq\n"
210 :: [v] "r" (rflags)
211 );
212}
213
214/** Return interrupt priority level.
215 *
216 * Return the current interrupt priority level.
217 *
218 * @return Current interrupt priority level.
219 *
220 */
221_NO_TRACE static inline ipl_t interrupts_read(void)
222{
223 return (ipl_t) read_rflags();
224}
225
226/** Enable interrupts.
227 *
228 * Enable interrupts and return the previous interrupt priority level.
229 *
230 * @return Old interrupt priority level.
231 *
232 */
233_NO_TRACE static inline ipl_t interrupts_enable(void)
234{
235 ipl_t ipl = interrupts_read();
236
237 asm volatile ("sti\n");
238
239 return ipl;
240}
241
242/** Disable interrupts.
243 *
244 * Disable interrupts and return the previous interrupt priority level.
245 *
246 * @return Old interrupt priority level.
247 *
248 */
249_NO_TRACE static inline ipl_t interrupts_disable(void)
250{
251 ipl_t ipl = interrupts_read();
252
253 asm volatile ("cli\n");
254
255 return ipl;
256}
257
258/** Restore interrupt priority level.
259 *
260 * Restore the previously save interrupt priority level.
261 *
262 * @param ipl Saved interrupt priority level.
263 *
264 */
265_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
266{
267 write_rflags((uint64_t) ipl);
268}
269
270/** Check interrupts state.
271 *
272 * @return True if interrupts are disabled.
273 *
274 */
275_NO_TRACE static inline bool interrupts_disabled(void)
276{
277 return ((read_rflags() & RFLAGS_IF) == 0);
278}
279
280/** Write to MSR */
281_NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
282{
283 asm volatile (
284 "wrmsr\n"
285 :: "c" (msr),
286 "a" ((uint32_t) (value)),
287 "d" ((uint32_t) (value >> 32))
288 );
289}
290
291_NO_TRACE static inline sysarg_t read_msr(uint32_t msr)
292{
293 uint32_t ax, dx;
294
295 asm volatile (
296 "rdmsr\n"
297 : "=a" (ax), "=d" (dx)
298 : "c" (msr)
299 );
300
301 return ((uint64_t) dx << 32) | ax;
302}
303
304/** Invalidate TLB Entry.
305 *
306 * @param addr Address on a page whose TLB entry is to be invalidated.
307 *
308 */
309_NO_TRACE static inline void invlpg(uintptr_t addr)
310{
311 asm volatile (
312 "invlpg %[addr]\n"
313 :: [addr] "m" (*((sysarg_t *) addr))
314 );
315}
316
317/** Load GDTR register from memory.
318 *
319 * @param gdtr_reg Address of memory from where to load GDTR.
320 *
321 */
322_NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
323{
324 asm volatile (
325 "lgdtq %[gdtr_reg]\n"
326 :: [gdtr_reg] "m" (*gdtr_reg)
327 );
328}
329
330/** Store GDTR register to memory.
331 *
332 * @param gdtr_reg Address of memory to where to load GDTR.
333 *
334 */
335_NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
336{
337 asm volatile (
338 "sgdtq %[gdtr_reg]\n"
339 :: [gdtr_reg] "m" (*gdtr_reg)
340 );
341}
342
343/** Load IDTR register from memory.
344 *
345 * @param idtr_reg Address of memory from where to load IDTR.
346 *
347 */
348_NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
349{
350 asm volatile (
351 "lidtq %[idtr_reg]\n"
352 :: [idtr_reg] "m" (*idtr_reg));
353}
354
355/** Load TR from descriptor table.
356 *
357 * @param sel Selector specifying descriptor of TSS segment.
358 *
359 */
360_NO_TRACE static inline void tr_load(uint16_t sel)
361{
362 asm volatile (
363 "ltr %[sel]"
364 :: [sel] "r" (sel)
365 );
366}
367
368#define GEN_READ_REG(reg) _NO_TRACE static inline sysarg_t read_ ##reg (void) \
369 { \
370 sysarg_t res; \
371 asm volatile ( \
372 "movq %%" #reg ", %[res]" \
373 : [res] "=r" (res) \
374 ); \
375 return res; \
376 }
377
378#define GEN_WRITE_REG(reg) _NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
379 { \
380 asm volatile ( \
381 "movq %[regn], %%" #reg \
382 :: [regn] "r" (regn) \
383 ); \
384 }
385
386GEN_READ_REG(cr0);
387GEN_WRITE_REG(cr0);
388GEN_READ_REG(cr2);
389GEN_READ_REG(cr3);
390GEN_WRITE_REG(cr3);
391GEN_READ_REG(cr4);
392GEN_WRITE_REG(cr4);
393
394GEN_READ_REG(dr0);
395GEN_READ_REG(dr1);
396GEN_READ_REG(dr2);
397GEN_READ_REG(dr3);
398GEN_READ_REG(dr6);
399GEN_READ_REG(dr7);
400
401GEN_WRITE_REG(dr0);
402GEN_WRITE_REG(dr1);
403GEN_WRITE_REG(dr2);
404GEN_WRITE_REG(dr3);
405GEN_WRITE_REG(dr6);
406GEN_WRITE_REG(dr7);
407
408extern void asm_delay_loop(uint32_t);
409extern void asm_fake_loop(uint32_t);
410
411extern uintptr_t int_0;
412extern uintptr_t int_1;
413extern uintptr_t int_2;
414extern uintptr_t int_3;
415extern uintptr_t int_4;
416extern uintptr_t int_5;
417extern uintptr_t int_6;
418extern uintptr_t int_7;
419extern uintptr_t int_8;
420extern uintptr_t int_9;
421extern uintptr_t int_10;
422extern uintptr_t int_11;
423extern uintptr_t int_12;
424extern uintptr_t int_13;
425extern uintptr_t int_14;
426extern uintptr_t int_15;
427extern uintptr_t int_16;
428extern uintptr_t int_17;
429extern uintptr_t int_18;
430extern uintptr_t int_19;
431extern uintptr_t int_20;
432extern uintptr_t int_21;
433extern uintptr_t int_22;
434extern uintptr_t int_23;
435extern uintptr_t int_24;
436extern uintptr_t int_25;
437extern uintptr_t int_26;
438extern uintptr_t int_27;
439extern uintptr_t int_28;
440extern uintptr_t int_29;
441extern uintptr_t int_30;
442extern uintptr_t int_31;
443extern uintptr_t int_32;
444extern uintptr_t int_33;
445extern uintptr_t int_34;
446extern uintptr_t int_35;
447extern uintptr_t int_36;
448extern uintptr_t int_37;
449extern uintptr_t int_38;
450extern uintptr_t int_39;
451extern uintptr_t int_40;
452extern uintptr_t int_41;
453extern uintptr_t int_42;
454extern uintptr_t int_43;
455extern uintptr_t int_44;
456extern uintptr_t int_45;
457extern uintptr_t int_46;
458extern uintptr_t int_47;
459extern uintptr_t int_48;
460extern uintptr_t int_49;
461extern uintptr_t int_50;
462extern uintptr_t int_51;
463extern uintptr_t int_52;
464extern uintptr_t int_53;
465extern uintptr_t int_54;
466extern uintptr_t int_55;
467extern uintptr_t int_56;
468extern uintptr_t int_57;
469extern uintptr_t int_58;
470extern uintptr_t int_59;
471extern uintptr_t int_60;
472extern uintptr_t int_61;
473extern uintptr_t int_62;
474extern uintptr_t int_63;
475
476extern void enable_l_apic_in_msr(void);
477
478#endif
479
480/** @}
481 */
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