source: mainline/kernel/arch/amd64/include/arch/asm.h@ 128359eb

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 128359eb was 128359eb, checked in by Martin Decky <martin@…>, 6 years ago

Replace get_stack_base() with builtin_frame_address(0)

The usage of an intrinsic function to obtain the current stack pointer
should provide the compuler more room for performance optimizations than
the hand-written (and volatile) inline assembly block.
  • Property mode set to 100644
File size: 9.7 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_amd64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_amd64_ASM_H_
36#define KERN_amd64_ASM_H_
37
38#include <config.h>
39#include <typedefs.h>
40#include <arch/cpu.h>
41#include <trace.h>
42
43#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
44
45_NO_TRACE static inline void cpu_sleep(void)
46{
47 asm volatile (
48 "hlt\n"
49 );
50}
51
52_NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
53{
54 while (true) {
55 asm volatile (
56 "hlt\n"
57 );
58 }
59}
60
61/** Byte from port
62 *
63 * Get byte from port
64 *
65 * @param port Port to read from
66 * @return Value read
67 *
68 */
69_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
70{
71 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
72 uint8_t val;
73
74 asm volatile (
75 "inb %w[port], %b[val]\n"
76 : [val] "=a" (val)
77 : [port] "d" (port)
78 );
79
80 return val;
81 } else
82 return (uint8_t) *port;
83}
84
85/** Word from port
86 *
87 * Get word from port
88 *
89 * @param port Port to read from
90 * @return Value read
91 *
92 */
93_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
94{
95 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
96 uint16_t val;
97
98 asm volatile (
99 "inw %w[port], %w[val]\n"
100 : [val] "=a" (val)
101 : [port] "d" (port)
102 );
103
104 return val;
105 } else
106 return (uint16_t) *port;
107}
108
109/** Double word from port
110 *
111 * Get double word from port
112 *
113 * @param port Port to read from
114 * @return Value read
115 *
116 */
117_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
118{
119 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
120 uint32_t val;
121
122 asm volatile (
123 "inl %w[port], %[val]\n"
124 : [val] "=a" (val)
125 : [port] "d" (port)
126 );
127
128 return val;
129 } else
130 return (uint32_t) *port;
131}
132
133/** Byte to port
134 *
135 * Output byte to port
136 *
137 * @param port Port to write to
138 * @param val Value to write
139 *
140 */
141_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
142{
143 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
144 asm volatile (
145 "outb %b[val], %w[port]\n"
146 :: [val] "a" (val), [port] "d" (port)
147 );
148 } else
149 *port = val;
150}
151
152/** Word to port
153 *
154 * Output word to port
155 *
156 * @param port Port to write to
157 * @param val Value to write
158 *
159 */
160_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
161{
162 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
163 asm volatile (
164 "outw %w[val], %w[port]\n"
165 :: [val] "a" (val), [port] "d" (port)
166 );
167 } else
168 *port = val;
169}
170
171/** Double word to port
172 *
173 * Output double word to port
174 *
175 * @param port Port to write to
176 * @param val Value to write
177 *
178 */
179_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
180{
181 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
182 asm volatile (
183 "outl %[val], %w[port]\n"
184 :: [val] "a" (val), [port] "d" (port)
185 );
186 } else
187 *port = val;
188}
189
190_NO_TRACE static inline uint64_t read_rflags(void)
191{
192 uint64_t rflags;
193
194 asm volatile (
195 "pushfq\n"
196 "popq %[v]\n"
197 : [v] "=r" (rflags)
198 );
199
200 return rflags;
201}
202
203_NO_TRACE static inline void write_rflags(uint64_t rflags)
204{
205 asm volatile (
206 "pushq %[v]\n"
207 "popfq\n"
208 :: [v] "r" (rflags)
209 );
210}
211
212/** Return interrupt priority level.
213 *
214 * Return the current interrupt priority level.
215 *
216 * @return Current interrupt priority level.
217 *
218 */
219_NO_TRACE static inline ipl_t interrupts_read(void)
220{
221 return (ipl_t) read_rflags();
222}
223
224/** Enable interrupts.
225 *
226 * Enable interrupts and return the previous interrupt priority level.
227 *
228 * @return Old interrupt priority level.
229 *
230 */
231_NO_TRACE static inline ipl_t interrupts_enable(void)
232{
233 ipl_t ipl = interrupts_read();
234
235 asm volatile ("sti\n");
236
237 return ipl;
238}
239
240/** Disable interrupts.
241 *
242 * Disable interrupts and return the previous interrupt priority level.
243 *
244 * @return Old interrupt priority level.
245 *
246 */
247_NO_TRACE static inline ipl_t interrupts_disable(void)
248{
249 ipl_t ipl = interrupts_read();
250
251 asm volatile ("cli\n");
252
253 return ipl;
254}
255
256/** Restore interrupt priority level.
257 *
258 * Restore the previously save interrupt priority level.
259 *
260 * @param ipl Saved interrupt priority level.
261 *
262 */
263_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
264{
265 write_rflags((uint64_t) ipl);
266}
267
268/** Check interrupts state.
269 *
270 * @return True if interrupts are disabled.
271 *
272 */
273_NO_TRACE static inline bool interrupts_disabled(void)
274{
275 return ((read_rflags() & RFLAGS_IF) == 0);
276}
277
278/** Write to MSR */
279_NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
280{
281 asm volatile (
282 "wrmsr\n"
283 :: "c" (msr),
284 "a" ((uint32_t) (value)),
285 "d" ((uint32_t) (value >> 32))
286 );
287}
288
289_NO_TRACE static inline sysarg_t read_msr(uint32_t msr)
290{
291 uint32_t ax, dx;
292
293 asm volatile (
294 "rdmsr\n"
295 : "=a" (ax), "=d" (dx)
296 : "c" (msr)
297 );
298
299 return ((uint64_t) dx << 32) | ax;
300}
301
302/** Invalidate TLB Entry.
303 *
304 * @param addr Address on a page whose TLB entry is to be invalidated.
305 *
306 */
307_NO_TRACE static inline void invlpg(uintptr_t addr)
308{
309 asm volatile (
310 "invlpg %[addr]\n"
311 :: [addr] "m" (*((sysarg_t *) addr))
312 );
313}
314
315/** Load GDTR register from memory.
316 *
317 * @param gdtr_reg Address of memory from where to load GDTR.
318 *
319 */
320_NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
321{
322 asm volatile (
323 "lgdtq %[gdtr_reg]\n"
324 :: [gdtr_reg] "m" (*gdtr_reg)
325 );
326}
327
328/** Store GDTR register to memory.
329 *
330 * @param gdtr_reg Address of memory to where to load GDTR.
331 *
332 */
333_NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
334{
335 asm volatile (
336 "sgdtq %[gdtr_reg]\n"
337 :: [gdtr_reg] "m" (*gdtr_reg)
338 );
339}
340
341/** Load IDTR register from memory.
342 *
343 * @param idtr_reg Address of memory from where to load IDTR.
344 *
345 */
346_NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
347{
348 asm volatile (
349 "lidtq %[idtr_reg]\n"
350 :: [idtr_reg] "m" (*idtr_reg));
351}
352
353/** Load TR from descriptor table.
354 *
355 * @param sel Selector specifying descriptor of TSS segment.
356 *
357 */
358_NO_TRACE static inline void tr_load(uint16_t sel)
359{
360 asm volatile (
361 "ltr %[sel]"
362 :: [sel] "r" (sel)
363 );
364}
365
366#define GEN_READ_REG(reg) _NO_TRACE static inline sysarg_t read_ ##reg (void) \
367 { \
368 sysarg_t res; \
369 asm volatile ( \
370 "movq %%" #reg ", %[res]" \
371 : [res] "=r" (res) \
372 ); \
373 return res; \
374 }
375
376#define GEN_WRITE_REG(reg) _NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
377 { \
378 asm volatile ( \
379 "movq %[regn], %%" #reg \
380 :: [regn] "r" (regn) \
381 ); \
382 }
383
384GEN_READ_REG(cr0);
385GEN_WRITE_REG(cr0);
386GEN_READ_REG(cr2);
387GEN_READ_REG(cr3);
388GEN_WRITE_REG(cr3);
389GEN_READ_REG(cr4);
390GEN_WRITE_REG(cr4);
391
392GEN_READ_REG(dr0);
393GEN_READ_REG(dr1);
394GEN_READ_REG(dr2);
395GEN_READ_REG(dr3);
396GEN_READ_REG(dr6);
397GEN_READ_REG(dr7);
398
399GEN_WRITE_REG(dr0);
400GEN_WRITE_REG(dr1);
401GEN_WRITE_REG(dr2);
402GEN_WRITE_REG(dr3);
403GEN_WRITE_REG(dr6);
404GEN_WRITE_REG(dr7);
405
406extern void asm_delay_loop(uint32_t);
407extern void asm_fake_loop(uint32_t);
408
409extern uintptr_t int_0;
410extern uintptr_t int_1;
411extern uintptr_t int_2;
412extern uintptr_t int_3;
413extern uintptr_t int_4;
414extern uintptr_t int_5;
415extern uintptr_t int_6;
416extern uintptr_t int_7;
417extern uintptr_t int_8;
418extern uintptr_t int_9;
419extern uintptr_t int_10;
420extern uintptr_t int_11;
421extern uintptr_t int_12;
422extern uintptr_t int_13;
423extern uintptr_t int_14;
424extern uintptr_t int_15;
425extern uintptr_t int_16;
426extern uintptr_t int_17;
427extern uintptr_t int_18;
428extern uintptr_t int_19;
429extern uintptr_t int_20;
430extern uintptr_t int_21;
431extern uintptr_t int_22;
432extern uintptr_t int_23;
433extern uintptr_t int_24;
434extern uintptr_t int_25;
435extern uintptr_t int_26;
436extern uintptr_t int_27;
437extern uintptr_t int_28;
438extern uintptr_t int_29;
439extern uintptr_t int_30;
440extern uintptr_t int_31;
441extern uintptr_t int_32;
442extern uintptr_t int_33;
443extern uintptr_t int_34;
444extern uintptr_t int_35;
445extern uintptr_t int_36;
446extern uintptr_t int_37;
447extern uintptr_t int_38;
448extern uintptr_t int_39;
449extern uintptr_t int_40;
450extern uintptr_t int_41;
451extern uintptr_t int_42;
452extern uintptr_t int_43;
453extern uintptr_t int_44;
454extern uintptr_t int_45;
455extern uintptr_t int_46;
456extern uintptr_t int_47;
457extern uintptr_t int_48;
458extern uintptr_t int_49;
459extern uintptr_t int_50;
460extern uintptr_t int_51;
461extern uintptr_t int_52;
462extern uintptr_t int_53;
463extern uintptr_t int_54;
464extern uintptr_t int_55;
465extern uintptr_t int_56;
466extern uintptr_t int_57;
467extern uintptr_t int_58;
468extern uintptr_t int_59;
469extern uintptr_t int_60;
470extern uintptr_t int_61;
471extern uintptr_t int_62;
472extern uintptr_t int_63;
473
474extern void enable_l_apic_in_msr(void);
475
476#endif
477
478/** @}
479 */
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