source: mainline/kernel.config@ b26db0c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b26db0c was 018d957e, checked in by Jakub Jermar <jakub@…>, 19 years ago

B+-tree implementation.
Currently supports only inserting and searching.

  • Property mode set to 100644
File size: 3.0 KB
RevLine 
[34722ee]1## General configuration directives
2
[9371c30]3# Architecture
[36e7b6c3]4@ "ia32" Intel IA-32
5@ "amd64" AMD64/Intel EM64T
6@ "ia64" Intel IA-64
[9371c30]7@ "mips32" MIPS 32-bit
8@ "ppc32" PowerPC 32-bit
[36e7b6c3]9@ "sparc64" Sun UltraSPARC
[9371c30]10! ARCH (choice)
11
12# IA32 Compiler
13@ "cross" Cross-compiler
14@ "native" Native
15! [ARCH=ia32] IA32_COMPILER (choice)
16% [ARCH=ia32] SAVEAS IA32_COMPILER COMPILER
17
18# AMD64 Compiler
19@ "cross" Cross-compiler
20@ "native" Native
21! [ARCH=amd64] AMD64_COMPILER (choice)
22% [ARCH=amd64] SAVEAS AMD64_COMPILER COMPILER
23
24# Compiler
25@ "cross" Cross-compiler
26@ "native" Native
27! [(ARCH!=amd64)&(ARCH!=ia32)] OTHER_COMPILER (choice)
28% [(ARCH!=amd64)&(ARCH!=ia32)] SAVEAS OTHER_COMPILER COMPILER
29
30
31# CPU type
32@ "pentium4" Pentium 4
33@ "pentium3" Pentium 3
34@ "athlon-xp" Athlon XP
35@ "athlon-mp" Athlon MP
36@ "prescott" Prescott
37! [ARCH=ia32] IA32_CPU (choice)
38
39# MIPS Machine Type
40@ "msim" MSIM Simulator
41@ "simics" Virtutech Simics simulator
42@ "lgxemul" GXEmul Little Endian
43@ "bgxemul" GXEmul Big Endian
44@ "indy" SGI Indy
45! [ARCH=mips32] MIPS_MACHINE (choice)
46
[bbf5657]47# Framebuffer support
[3debedec]48! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)] CONFIG_FB (y/n)
[bbf5657]49
[944b15c]50# Support for SMP
51! [ARCH=ia32|ARCH=amd64] CONFIG_SMP (y/n)
52
53# Improved support for hyperthreading
54! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n)
55
[04225a7]56# Simics BIOS AP boot fix
57! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n)
58
[944b15c]59# Lazy FPU context switching
[9e1c942]60! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64] CONFIG_FPU_LAZY (y/n)
[944b15c]61
[91d5ad6]62# Power off on halt
63! [ARCH=ppc32] CONFIG_POWEROFF (y/n)
64
[34722ee]65## Debugging configuration directives
66
67# General debuging and assert checking
68! CONFIG_DEBUG (y/n)
69
70# Deadlock detection support for spinlocks
[b4cad8b2]71! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n)
[34722ee]72
[4e49572]73# Watchpoint on rewriting AS with zero
[23d22eb]74! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=ia32)] CONFIG_DEBUG_AS_WATCHPOINT (y/n)
[4e49572]75
[8d25b44]76# Save all interrupt registers
[53f9821]77! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=mips32|ARCH=ia32)] CONFIG_DEBUG_ALLREGS (y/n)
[8d25b44]78
[34722ee]79## Run-time configuration directives
80
81# Kernel test type
82@ "" No test
[9a2d6e1]83@ "atomic/atomic1" Test of atomic operations.
[018d957e]84@ "btree/btree1" B-tree test.
[34722ee]85@ "synch/rwlock1" Read write test 1
86@ "synch/rwlock2" Read write test 2
87@ "synch/rwlock3" Read write test 3
88@ "synch/rwlock4" Read write test 4
89@ "synch/rwlock5" Read write test 5
90@ "synch/semaphore1" Semaphore test 1
91@ "synch/semaphore2" Sempahore test 2
[9e1c942]92@ [ARCH=ia32|ARCH=amd64|ARCH=ia64] "fpu/fpu1" Intel fpu test 1
[795ff98]93@ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1
[a276c56]94@ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1
[34722ee]95@ "print/print1" Printf test 1
[3887b105]96@ "thread/thread1" Thread test 1
[d43d2f7]97@ "mm/mapping1" Mapping test 1
[f275cb3]98@ "mm/falloc1" Frame Allocation test 1
[078a0a1]99@ "mm/falloc2" Frame Allocation test 2
[4a5b2b0e]100@ "mm/slab1" SLAB test1 - No CPU-cache
101@ "mm/slab2" SLAB test2 - SMP CPU cache
[4a2b52f]102@ "fault/fault1" Write to NULL (maybe page fault)
[bdab828]103@ [ARCH=ia64] "mm/purge1" Itanium TLB purge test
[e07fe0c]104@ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test
[34722ee]105! CONFIG_TEST (choice)
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