1 | /*
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2 | * Copyright (C) 2006 Ondrej Palkovsky
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 |
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29 | /** IRQ notification framework
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30 | *
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31 | * This framework allows applications to register to receive a notification
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32 | * when interrupt is detected. The application may provide a simple 'top-half'
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33 | * handler as part of its registration, which can perform simple operations
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34 | * (read/write port/memory, add information to notification ipc message).
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35 | *
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36 | * The structure of a notification message is as follows:
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37 | * - METHOD: IPC_M_INTERRUPT
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38 | * - ARG1: interrupt number
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39 | * - ARG2: payload modified by a 'top-half' handler
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40 | * - ARG3: interrupt counter (may be needed to assure correct order
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41 | * in multithreaded drivers)
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42 | */
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43 |
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44 | #include <arch.h>
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45 | #include <mm/slab.h>
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46 | #include <errno.h>
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47 | #include <ipc/ipc.h>
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48 | #include <ipc/irq.h>
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49 | #include <atomic.h>
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50 | #include <syscall/copy.h>
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51 | #include <console/console.h>
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52 |
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53 | typedef struct {
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54 | SPINLOCK_DECLARE(lock);
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55 | answerbox_t *box;
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56 | irq_code_t *code;
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57 | atomic_t counter;
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58 | } ipc_irq_t;
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59 |
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60 |
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61 | static ipc_irq_t *irq_conns = NULL;
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62 | static int irq_conns_size;
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63 |
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64 | #include <print.h>
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65 | /* Execute code associated with IRQ notification */
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66 | static void code_execute(call_t *call, irq_code_t *code)
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67 | {
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68 | int i;
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69 |
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70 | if (!code)
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71 | return;
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72 |
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73 | for (i=0; i < code->cmdcount;i++) {
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74 | switch (code->cmds[i].cmd) {
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75 | case CMD_MEM_READ_1:
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76 | IPC_SET_ARG2(call->data, *((__u8 *)code->cmds[i].addr));
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77 | break;
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78 | case CMD_MEM_READ_2:
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79 | IPC_SET_ARG2(call->data, *((__u16 *)code->cmds[i].addr));
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80 | break;
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81 | case CMD_MEM_READ_4:
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82 | IPC_SET_ARG2(call->data, *((__u32 *)code->cmds[i].addr));
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83 | break;
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84 | case CMD_MEM_READ_8:
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85 | IPC_SET_ARG2(call->data, *((__u64 *)code->cmds[i].addr));
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86 | break;
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87 | case CMD_MEM_WRITE_1:
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88 | *((__u8 *)code->cmds[i].addr) = code->cmds[i].value;
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89 | break;
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90 | case CMD_MEM_WRITE_2:
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91 | *((__u16 *)code->cmds[i].addr) = code->cmds[i].value;
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92 | break;
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93 | case CMD_MEM_WRITE_4:
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94 | *((__u32 *)code->cmds[i].addr) = code->cmds[i].value;
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95 | break;
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96 | case CMD_MEM_WRITE_8:
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97 | *((__u64 *)code->cmds[i].addr) = code->cmds[i].value;
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98 | break;
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99 | #if defined(ia32) || defined(amd64)
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100 | case CMD_PORT_READ_1:
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101 | IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr));
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102 | break;
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103 | case CMD_PORT_WRITE_1:
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104 | outb((long)code->cmds[i].addr, code->cmds[i].value);
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105 | break;
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106 | #endif
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107 | #if defined(ia64)
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108 | case CMD_IA64_GETCHAR:
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109 | IPC_SET_ARG2(call->data, _getc(&ski_uconsole));
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110 | break;
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111 | #endif
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112 | default:
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113 | break;
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114 | }
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115 | }
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116 | }
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117 |
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118 | static void code_free(irq_code_t *code)
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119 | {
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120 | if (code) {
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121 | free(code->cmds);
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122 | free(code);
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123 | }
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124 | }
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125 |
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126 | static irq_code_t * code_from_uspace(irq_code_t *ucode)
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127 | {
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128 | irq_code_t *code;
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129 | irq_cmd_t *ucmds;
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130 | int rc;
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131 |
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132 | code = malloc(sizeof(*code), 0);
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133 | rc = copy_from_uspace(code, ucode, sizeof(*code));
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134 | if (rc != 0) {
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135 | free(code);
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136 | return NULL;
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137 | }
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138 |
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139 | if (code->cmdcount > IRQ_MAX_PROG_SIZE) {
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140 | free(code);
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141 | return NULL;
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142 | }
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143 | ucmds = code->cmds;
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144 | code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0);
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145 | rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount));
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146 | if (rc != 0) {
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147 | free(code->cmds);
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148 | free(code);
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149 | return NULL;
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150 | }
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151 |
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152 | return code;
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153 | }
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154 |
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155 | /** Unregister task from irq */
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156 | void ipc_irq_unregister(answerbox_t *box, int irq)
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157 | {
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158 | ipl_t ipl;
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159 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL;
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160 |
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161 | ipl = interrupts_disable();
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162 | spinlock_lock(&irq_conns[mq].lock);
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163 | if (irq_conns[mq].box == box) {
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164 | irq_conns[mq].box = NULL;
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165 | code_free(irq_conns[mq].code);
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166 | irq_conns[mq].code = NULL;
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167 | }
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168 |
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169 | spinlock_unlock(&irq_conns[mq].lock);
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170 | interrupts_restore(ipl);
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171 | }
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172 |
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173 | /** Register an answerbox as a receiving end of interrupts notifications */
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174 | int ipc_irq_register(answerbox_t *box, int irq, irq_code_t *ucode)
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175 | {
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176 | ipl_t ipl;
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177 | irq_code_t *code;
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178 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL;
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179 |
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180 | ASSERT(irq_conns);
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181 |
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182 | if (ucode) {
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183 | code = code_from_uspace(ucode);
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184 | if (!code)
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185 | return EBADMEM;
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186 | } else
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187 | code = NULL;
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188 |
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189 | ipl = interrupts_disable();
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190 | spinlock_lock(&irq_conns[mq].lock);
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191 |
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192 | if (irq_conns[mq].box) {
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193 | spinlock_unlock(&irq_conns[mq].lock);
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194 | interrupts_restore(ipl);
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195 | code_free(code);
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196 | return EEXISTS;
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197 | }
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198 | irq_conns[mq].box = box;
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199 | irq_conns[mq].code = code;
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200 | atomic_set(&irq_conns[mq].counter, 0);
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201 | spinlock_unlock(&irq_conns[mq].lock);
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202 | interrupts_restore(ipl);
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203 |
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204 | return 0;
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205 | }
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206 |
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207 | /** Add call to proper answerbox queue
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208 | *
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209 | * Assume irq_conns[mq].lock is locked */
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210 | static void send_call(int mq, call_t *call)
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211 | {
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212 | spinlock_lock(&irq_conns[mq].box->irq_lock);
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213 | list_append(&call->link, &irq_conns[mq].box->irq_notifs);
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214 | spinlock_unlock(&irq_conns[mq].box->irq_lock);
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215 |
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216 | waitq_wakeup(&irq_conns[mq].box->wq, 0);
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217 | }
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218 |
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219 | /** Send notification message
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220 | *
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221 | */
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222 | void ipc_irq_send_msg(int irq, __native a2, __native a3)
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223 | {
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224 | call_t *call;
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225 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL;
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226 |
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227 | spinlock_lock(&irq_conns[mq].lock);
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228 |
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229 | if (irq_conns[mq].box) {
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230 | call = ipc_call_alloc(FRAME_ATOMIC);
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231 | if (!call) {
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232 | spinlock_unlock(&irq_conns[mq].lock);
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233 | return;
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234 | }
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235 | call->flags |= IPC_CALL_NOTIF;
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236 | IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);
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237 | IPC_SET_ARG1(call->data, irq);
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238 | IPC_SET_ARG2(call->data, a2);
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239 | IPC_SET_ARG3(call->data, a3);
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240 |
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241 | send_call(mq, call);
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242 | }
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243 | spinlock_unlock(&irq_conns[mq].lock);
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244 | }
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245 |
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246 | /** Notify process that an irq had happend
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247 | *
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248 | * We expect interrupts to be disabled
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249 | */
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250 | void ipc_irq_send_notif(int irq)
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251 | {
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252 | call_t *call;
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253 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL;
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254 |
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255 | ASSERT(irq_conns);
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256 | spinlock_lock(&irq_conns[mq].lock);
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257 |
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258 | if (irq_conns[mq].box) {
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259 | call = ipc_call_alloc(FRAME_ATOMIC);
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260 | if (!call) {
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261 | spinlock_unlock(&irq_conns[mq].lock);
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262 | return;
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263 | }
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264 | call->flags |= IPC_CALL_NOTIF;
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265 | IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);
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266 | IPC_SET_ARG1(call->data, irq);
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267 | IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[mq].counter));
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268 |
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269 | /* Execute code to handle irq */
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270 | code_execute(call, irq_conns[mq].code);
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271 |
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272 | send_call(mq, call);
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273 | }
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274 |
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275 | spinlock_unlock(&irq_conns[mq].lock);
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276 | }
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277 |
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278 |
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279 | /** Initialize table of interrupt handlers
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280 | *
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281 | * @param irqcount Count of required hardware IRQs to be supported
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282 | */
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283 | void ipc_irq_make_table(int irqcount)
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284 | {
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285 | int i;
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286 |
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287 | irqcount += IPC_IRQ_RESERVED_VIRTUAL;
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288 |
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289 | irq_conns_size = irqcount;
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290 | irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0);
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291 | for (i=0; i < irqcount; i++) {
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292 | spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock");
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293 | irq_conns[i].box = NULL;
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294 | irq_conns[i].code = NULL;
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295 | }
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296 | }
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297 |
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298 | /** Disconnect all irq's notifications
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299 | *
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300 | * TODO: It may be better to do some linked list, so that
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301 | * we wouldn't need to go through whole array every cleanup
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302 | */
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303 | void ipc_irq_cleanup(answerbox_t *box)
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304 | {
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305 | int i;
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306 | ipl_t ipl;
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307 |
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308 | for (i=0; i < irq_conns_size; i++) {
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309 | ipl = interrupts_disable();
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310 | spinlock_lock(&irq_conns[i].lock);
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311 | if (irq_conns[i].box == box)
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312 | irq_conns[i].box = NULL;
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313 | spinlock_unlock(&irq_conns[i].lock);
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314 | interrupts_restore(ipl);
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315 | }
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316 | }
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