| 1 | Memory management
|
|---|
| 2 | =================
|
|---|
| 3 |
|
|---|
| 4 | 1. Virtual Address Translation
|
|---|
| 5 |
|
|---|
| 6 | 1.1 Hierarchical 4-level per address space page tables
|
|---|
| 7 |
|
|---|
| 8 | SPARTAN kernel deploys generic interface for 4-level page tables
|
|---|
| 9 | for these architectures: amd64, ia32, mips32 and ppc32. In this
|
|---|
| 10 | setting, page tables are hierarchical and are not shared by
|
|---|
| 11 | address spaces (i.e. one set of page tables per address space).
|
|---|
| 12 |
|
|---|
| 13 |
|
|---|
| 14 | VADDR
|
|---|
| 15 | +-----------------------------------------------------------------------------+
|
|---|
| 16 | | PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET |
|
|---|
| 17 | +-----------------------------------------------------------------------------+
|
|---|
| 18 |
|
|---|
| 19 |
|
|---|
| 20 | PTL0 PTL1 PTL2 PTL3
|
|---|
| 21 | +--------+ +--------+ +--------+ +--------+
|
|---|
| 22 | | | | | | PTL3 | -----\ | |
|
|---|
| 23 | | | | | +--------+ | | |
|
|---|
| 24 | | | +--------+ | | | | |
|
|---|
| 25 | | | | PTL2 | -----\ | | | | |
|
|---|
| 26 | | | +--------+ | | | | | |
|
|---|
| 27 | | | | | | | | | +--------+
|
|---|
| 28 | +--------+ | | | | | | | FRAME |
|
|---|
| 29 | | PTL1 | -----\ | | | | | | +--------+
|
|---|
| 30 | +--------+ | | | | | | | | |
|
|---|
| 31 | | | | | | | | | | | |
|
|---|
| 32 | | | | | | | | | | | |
|
|---|
| 33 | +--------+ \----> +--------+ \----> +--------+ \----> +--------+
|
|---|
| 34 | ^
|
|---|
| 35 | |
|
|---|
| 36 | |
|
|---|
| 37 | +--------+
|
|---|
| 38 | | PTL0 |
|
|---|
| 39 | +--------+
|
|---|
| 40 |
|
|---|
| 41 |
|
|---|
| 42 | PTL0 Page Table Level 0 (Page Directory)
|
|---|
| 43 | PTL1 Page Table Level 1
|
|---|
| 44 | PTL2 Page Table Level 2
|
|---|
| 45 | PTL3 Page Table Level 3
|
|---|
| 46 |
|
|---|
| 47 | PTL0_INDEX Index into PTL0
|
|---|
| 48 | PTL1_INDEX Index into PTL1
|
|---|
| 49 | PTL2_INDEX Index into PTL2
|
|---|
| 50 | PTL3_INDEX Index into PTL3
|
|---|
| 51 |
|
|---|
| 52 | VADDR Virtual address for which mapping is looked up
|
|---|
| 53 | FRAME Physical address of memory frame to which VADDR is mapped
|
|---|
| 54 |
|
|---|
| 55 |
|
|---|
| 56 | On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are
|
|---|
| 57 | left out. TLB-only architectures are to define custom format for software page
|
|---|
| 58 | tables.
|
|---|
| 59 |
|
|---|
| 60 |
|
|---|
| 61 |
|
|---|
| 62 | 1.2 Single global page hash table
|
|---|
| 63 |
|
|---|
| 64 | Generic page hash table interface is deployed on 64-bit architectures without
|
|---|
| 65 | implied hardware support for hierarchical page tables, i.e. ia64 and sparc64.
|
|---|
| 66 | There is only one global page hash table in the system shared by all address
|
|---|
| 67 | spaces.
|
|---|
