source: mainline/boot/arch/sparc64/loader/asm.S@ d2e9c47

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d2e9c47 was 1eb154f, checked in by Jakub Jermar <jakub@…>, 17 years ago

Don't make any assumptions about the contents of the I-cache in sparc64
loader and before passing control to the kernel, invalidate the I-cache.

  • Property mode set to 100644
File size: 3.4 KB
Line 
1#
2# Copyright (c) 2006 Martin Decky
3# Copyright (c) 2006 Jakub Jermar
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions
8# are met:
9#
10# - Redistributions of source code must retain the above copyright
11# notice, this list of conditions and the following disclaimer.
12# - Redistributions in binary form must reproduce the above copyright
13# notice, this list of conditions and the following disclaimer in the
14# documentation and/or other materials provided with the distribution.
15# - The name of the author may not be used to endorse or promote products
16# derived from this software without specific prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29
30#include <stack.h>
31#include <register.h>
32
33.text
34
35.global halt
36.global memcpy
37.global jump_to_kernel
38
39halt:
40 b halt
41 nop
42
43memcpy:
44 .register %g2, #scratch
45 .register %g3, #scratch
46 add %o1, 7, %g1
47 and %g1, -8, %g1
48 cmp %o1, %g1
49 be,pn %xcc, 3f
50 add %o0, 7, %g1
51 mov 0, %g3
520:
53 brz,pn %o2, 2f
54 mov 0, %g2
551:
56 ldub [%g3 + %o1], %g1
57 add %g2, 1, %g2
58 cmp %o2, %g2
59 stb %g1, [%g3 + %o0]
60 bne,pt %xcc, 1b
61 mov %g2, %g3
622:
63 jmp %o7 + 8 ! exit point
64 mov %o1, %o0
653:
66 and %g1, -8, %g1
67 cmp %o0, %g1
68 bne,pt %xcc, 0b
69 mov 0, %g3
70 srlx %o2, 3, %g4
71 brz,pn %g4, 5f
72 mov 0, %g5
734:
74 sllx %g3, 3, %g2
75 add %g5, 1, %g3
76 ldx [%o1 + %g2], %g1
77 mov %g3, %g5
78 cmp %g4, %g3
79 bne,pt %xcc, 4b
80 stx %g1, [%o0 + %g2]
815:
82 and %o2, 7, %o2
83 brz,pn %o2, 2b
84 sllx %g4, 3, %g1
85 mov 0, %g2
86 add %g1, %o0, %o0
87 add %g1, %o1, %g4
88 mov 0, %g3
896:
90 ldub [%g2 + %g4], %g1
91 stb %g1, [%g2 + %o0]
92 add %g3, 1, %g2
93 cmp %o2, %g2
94 bne,pt %xcc, 6b
95 mov %g2, %g3
96
97 jmp %o7 + 8 ! exit point
98 mov %o1, %o0
99
100jump_to_kernel:
101 /*
102 * We have copied code and now we need to guarantee cache coherence.
103 * 1. Make sure that the code we have moved has drained to main memory.
104 * 2. Invalidate I-cache.
105 * 3. Flush instruction pipeline.
106 */
107 call icache_flush
108 membar #StoreStore
109 flush %i7
110
111 mov %o0, %l1
112 mov %o1, %o0
113 mov %o2, %o1
114 mov %o3, %o2
115 jmp %l1 ! jump to kernel
116 nop
117
118#define ICACHE_SIZE 8192
119#define ICACHE_LINE_SIZE 32
120#define ICACHE_SET_BIT (1 << 13)
121#define ASI_ICACHE_TAG 0x67
122
123# Flush I-cache
124icache_flush:
125 set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1
126 stxa %g0, [%g1] ASI_ICACHE_TAG
1270: membar #Sync
128 subcc %g1, ICACHE_LINE_SIZE, %g1
129 bnz,pt %xcc, 0b
130 stxa %g0, [%g1] ASI_ICACHE_TAG
131 membar #Sync
132 retl
133 ! SF Erratum #51
134 nop
135
136.global ofw
137ofw:
138 save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
139 set ofw_cif, %l0
140 ldx [%l0], %l0
141
142 rdpr %pstate, %l1
143 and %l1, ~PSTATE_AM_BIT, %l2
144 wrpr %l2, 0, %pstate
145
146 jmpl %l0, %o7
147 mov %i0, %o0
148
149 wrpr %l1, 0, %pstate
150
151 ret
152 restore %o0, 0, %o0
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