1 | #
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2 | # Copyright (c) 2006 Martin Decky
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3 | # All rights reserved.
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4 | #
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5 | # Redistribution and use in source and binary forms, with or without
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6 | # modification, are permitted provided that the following conditions
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7 | # are met:
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8 | #
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9 | # - Redistributions of source code must retain the above copyright
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10 | # notice, this list of conditions and the following disclaimer.
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11 | # - Redistributions in binary form must reproduce the above copyright
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12 | # notice, this list of conditions and the following disclaimer in the
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13 | # documentation and/or other materials provided with the distribution.
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14 | # - The name of the author may not be used to endorse or promote products
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15 | # derived from this software without specific prior written permission.
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16 | #
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17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | #
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28 |
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29 | #include <arch/arch.h>
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30 | #include <arch/regname.h>
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31 |
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32 | .macro SMC_COHERENCY addr
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33 | dcbst 0, \addr
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34 | sync
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35 | icbi 0, \addr
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36 | sync
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37 | isync
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38 | .endm
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39 |
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40 | .macro FLUSH_DCACHE addr
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41 | dcbst 0, \addr
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42 | sync
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43 | isync
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44 | .endm
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45 |
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46 | .macro TLB_FLUSH reg
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47 | li \reg, 0
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48 | sync
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49 |
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50 | .rept 64
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51 | tlbie \reg
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52 | addi \reg, \reg, 0x1000
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53 | .endr
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54 |
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55 | eieio
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56 | tlbsync
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57 | sync
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58 | .endm
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59 |
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60 | .macro BAT_COMPUTE base size mask lower upper
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61 | # less than 128 KB -> no BAT
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62 |
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63 | lis \upper, 0x0002
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64 | cmpw \size, \upper
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65 | blt no_bat
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66 |
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67 | # mask = total >> 18
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68 |
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69 | li \upper, 18
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70 | srw \mask, \size, \upper
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71 |
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72 | # create Block Length mask by replicating
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73 | # the leading logical one 14 times
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74 |
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75 | li \upper, 14
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76 | mtctr \mask
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77 | li \upper, 1
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78 |
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79 | 0:
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80 | # mask = (mask >> 1) | mask
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81 |
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82 | srw \lower, \mask, \upper
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83 | or \mask, \mask, \lower
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84 |
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85 | bdnz 0b
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86 |
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87 | # mask = mask & 0x07ff
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88 | # (BAT can map up to 256 MB)
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89 |
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90 | andi. \mask, \mask, 0x07ff
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91 |
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92 | # mask = (mask << 2) | 0x0002
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93 | # (priviledged access only)
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94 |
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95 | li \upper, 2
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96 | slw \mask, \mask, \upper
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97 | ori \mask, \mask, 0x0002
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98 |
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99 | lis \upper, (0x8000 + \base)
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100 | or \upper, \upper, \mask
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101 |
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102 | lis \lower, \base
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103 | ori \lower, \lower, 0x0002
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104 | .endm
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105 |
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106 | .global start
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107 | .global halt
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108 | .global jump_to_kernel
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109 | .global real_mode
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110 |
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111 | .section BOOTSTRAP, "ax"
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112 |
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113 | start:
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114 | lis r4, ofw_cif@ha
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115 | addi r4, r4, ofw_cif@l
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116 | stw r5, 0(r4)
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117 |
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118 | bl ofw_init
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119 | b bootstrap
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120 |
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121 | .text
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122 |
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123 | halt:
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124 | b halt
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125 |
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126 | jump_to_kernel:
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127 |
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128 | # arguments:
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129 | # r3 = bootinfo (physical address)
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130 | # r4 = translate table (physical address)
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131 | # r5 = pages to translate
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132 | # r6 = real mode meeting point (physical address)
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133 |
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134 | # disable interrupts
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135 |
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136 | mfmsr r31
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137 | rlwinm r31, r31, 0, 17, 15
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138 | mtmsr r31
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139 |
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140 | # set real mode meeting point physical address
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141 |
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142 | mtspr srr0, r6
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143 |
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144 | # jump to real_mode
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145 |
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146 | mfmsr r31
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147 | lis r30, ~0@h
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148 | ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
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149 | and r31, r31, r30
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150 | mtspr srr1, r31
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151 |
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152 | sync
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153 | isync
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154 | rfi
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155 |
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156 | .section REALMODE, "ax"
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157 |
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158 | .align PAGE_WIDTH
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159 | real_mode:
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160 |
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161 | # arguments:
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162 | # r3 = bootinfo (physical address)
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163 | # r4 = translate table (physical address)
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164 | # r5 = pages to translate
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165 |
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166 | # move the images of components to the proper
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167 | # location using the translate table
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168 |
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169 | li r31, PAGE_SIZE >> 2
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170 | li r30, 0
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171 |
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172 | page_copy:
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173 |
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174 | cmpwi r5, 0
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175 | beq copy_end
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176 |
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177 | mtctr r31
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178 | lwz r29, 0(r4)
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179 |
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180 | copy_loop:
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181 |
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182 | lwz r28, 0(r29)
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183 | stw r28, 0(r30)
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184 |
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185 | SMC_COHERENCY r30
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186 |
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187 | addi r29, r29, 4
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188 | addi r30, r30, 4
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189 |
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190 | bdnz copy_loop
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191 |
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192 | addi r4, r4, 4
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193 | subi r5, r5, 1
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194 | b page_copy
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195 |
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196 | copy_end:
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197 |
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198 | # initially fill segment registers
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199 |
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200 | li r31, 0
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201 |
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202 | li r29, 8
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203 | mtctr r29
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204 | li r30, 0 # ASID 0 (VSIDs 0 .. 7)
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205 |
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206 | seg_fill_uspace:
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207 |
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208 | mtsrin r30, r31
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209 | addi r30, r30, 1
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210 | addis r31, r31, 0x1000 # move to next SR
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211 |
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212 | bdnz seg_fill_uspace
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213 |
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214 | li r29, 8
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215 | mtctr r29
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216 | lis r30, 0x4000 # priviledged access only
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217 | ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
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218 |
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219 | seg_fill_kernel:
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220 |
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221 | mtsrin r30, r31
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222 | addi r30, r30, 1
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223 | addis r31, r31, 0x1000 # move to next SR
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224 |
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225 | bdnz seg_fill_kernel
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226 |
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227 | # invalidate block address translation registers
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228 |
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229 | li r30, 0
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230 |
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231 | mtspr ibat0u, r30
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232 | mtspr ibat0l, r30
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233 |
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234 | mtspr ibat1u, r30
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235 | mtspr ibat1l, r30
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236 |
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237 | mtspr ibat2u, r30
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238 | mtspr ibat2l, r30
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239 |
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240 | mtspr ibat3u, r30
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241 | mtspr ibat3l, r30
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242 |
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243 | mtspr dbat0u, r30
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244 | mtspr dbat0l, r30
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245 |
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246 | mtspr dbat1u, r30
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247 | mtspr dbat1l, r30
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248 |
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249 | mtspr dbat2u, r30
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250 | mtspr dbat2l, r30
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251 |
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252 | mtspr dbat3u, r30
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253 | mtspr dbat3l, r30
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254 |
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255 | # create empty Page Hash Table
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256 | # on top of memory, size 64 KB
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257 |
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258 | lwz r31, 4(r3) # r31 = memory size
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259 |
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260 | lis r30, 65536@h
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261 | ori r30, r30, 65536@l # r30 = 65536
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262 |
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263 | subi r29, r30, 1 # r29 = 65535
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264 |
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265 | sub r31, r31, r30
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266 | andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
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267 |
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268 | mtsdr1 r31
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269 |
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270 | li r29, 2
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271 | srw r30, r30, r29 # r30 = 16384
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272 | li r29, 0
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273 |
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274 | pht_clear:
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275 |
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276 | # write zeroes
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277 |
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278 | stw r29, 0(r31)
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279 | FLUSH_DCACHE r31
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280 |
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281 | addi r31, r31, 4
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282 | subi r30, r30, 4
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283 |
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284 | cmpwi r30, 0
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285 | beq clear_end
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286 |
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287 | bdnz pht_clear
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288 |
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289 | clear_end:
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290 |
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291 | # create BAT identity mapping
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292 |
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293 | lwz r31, 4(r3) # r31 = memory size
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294 |
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295 | lis r30, 268435456@h
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296 | ori r30, r30, 268435456@l # r30 = 256 MB
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297 |
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298 | # BAT0
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299 |
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300 | # r29 = min(r31, r30)
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301 |
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302 | cmpw r31, r30
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303 | blt bat0_r31
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304 |
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305 | mr r29, r30
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306 | b bat0_r30
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307 |
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308 | bat0_r31:
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309 |
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310 | mr r29, r31
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311 |
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312 | bat0_r30:
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313 |
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314 | BAT_COMPUTE 0x0000 r29 r28 r27 r26
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315 | mtspr ibat0u, r26
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316 | mtspr ibat0l, r27
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317 |
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318 | mtspr dbat0u, r26
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319 | mtspr dbat0l, r27
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320 |
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321 | # BAT1
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322 |
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323 | sub r31, r31, r29 # r31 = r31 - r29
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324 |
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325 | # r29 = min(r31, r30)
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326 |
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327 | cmpw r31, r30
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328 | blt bat1_r31
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329 |
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330 | mr r29, r30
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331 | b bat1_r30
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332 |
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333 | bat1_r31:
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334 |
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335 | mr r29, r31
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336 |
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337 | bat1_r30:
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338 |
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339 | BAT_COMPUTE 0x1000 r29 r28 r27 r26
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340 | mtspr ibat1u, r26
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341 | mtspr ibat1l, r27
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342 |
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343 | mtspr dbat1u, r26
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344 | mtspr dbat1l, r27
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345 |
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346 | # BAT2
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347 |
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348 | sub r31, r31, r29 # r31 = r31 - r29
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349 |
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350 | # r29 = min(r31, r30)
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351 |
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352 | cmpw r31, r30
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353 | blt bat2_r31
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354 |
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355 | mr r29, r30
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356 | b bat2_r30
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357 |
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358 | bat2_r31:
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359 |
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360 | mr r29, r31
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361 |
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362 | bat2_r30:
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363 |
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364 | BAT_COMPUTE 0x2000 r29 r28 r27 r26
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365 | mtspr ibat2u, r26
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366 | mtspr ibat2l, r27
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367 |
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368 | mtspr dbat2u, r26
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369 | mtspr dbat2l, r27
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370 |
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371 | # BAT3
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372 |
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373 | sub r31, r31, r29 # r31 = r31 - r29
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374 |
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375 | # r29 = min(r31, r30)
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376 |
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377 | cmpw r31, r30
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378 | blt bat3_r31
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379 |
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380 | mr r29, r30
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381 | b bat3_r30
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382 |
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383 | bat3_r31:
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384 |
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385 | mr r29, r31
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386 |
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387 | bat3_r30:
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388 |
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389 | BAT_COMPUTE 0x3000 r29 r28 r27 r26
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390 | mtspr ibat3u, r26
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391 | mtspr ibat3l, r27
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392 |
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393 | mtspr dbat3u, r26
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394 | mtspr dbat3l, r27
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395 |
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396 | no_bat:
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397 |
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398 | # flush TLB
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399 |
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400 | TLB_FLUSH r31
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401 |
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402 | # start the kernel
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403 | #
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404 | # pc = PA2KA(BOOT_OFFSET)
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405 | # r3 = bootinfo (physical address)
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406 | # sprg0 = BOOT_OFFSET
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407 | # sprg3 = physical memory size
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408 | # sp = 0 (enforces the usage of sprg0 as exception stack)
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409 |
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410 | lis r31, PA2KA(BOOT_OFFSET)@ha
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411 | addi r31, r31, PA2KA(BOOT_OFFSET)@l
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412 | mtspr srr0, r31
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413 |
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414 | lis r31, BOOT_OFFSET@ha
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415 | addi r31, r31, BOOT_OFFSET@l
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416 | mtsprg0 r31
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417 |
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418 | # bootinfo starts with a 64 bit integer containing
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419 | # the physical memory size, get the lower 4 bytes
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420 |
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421 | lwz r31, 4(r3)
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422 | mtsprg3 r31
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423 |
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424 | li sp, 0
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425 |
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426 | mfmsr r31
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427 | ori r31, r31, (msr_ir | msr_dr)@l
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428 | mtspr srr1, r31
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429 |
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430 | sync
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431 | isync
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432 | rfi
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