source: mainline/boot/arch/ppc32/src/asm.S@ dd93bb2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since dd93bb2 was b372015, checked in by Martin Decky <martin@…>, 14 years ago

ppc32: add support for up to 1024 MB of physical memory by using all four BAT pairs

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File size: 7.1 KB
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1#
2# Copyright (c) 2006 Martin Decky
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/arch.h>
30#include <arch/regname.h>
31
32.macro SMC_COHERENCY addr
33 dcbst 0, \addr
34 sync
35 icbi 0, \addr
36 sync
37 isync
38.endm
39
40.macro FLUSH_DCACHE addr
41 dcbst 0, \addr
42 sync
43 isync
44.endm
45
46.macro TLB_FLUSH reg
47 li \reg, 0
48 sync
49
50 .rept 64
51 tlbie \reg
52 addi \reg, \reg, 0x1000
53 .endr
54
55 eieio
56 tlbsync
57 sync
58.endm
59
60.macro BAT_COMPUTE base size mask lower upper
61 # less than 128 KB -> no BAT
62
63 lis \upper, 0x0002
64 cmpw \size, \upper
65 blt no_bat
66
67 # mask = total >> 18
68
69 li \upper, 18
70 srw \mask, \size, \upper
71
72 # create Block Length mask by replicating
73 # the leading logical one 14 times
74
75 li \upper, 14
76 mtctr \mask
77 li \upper, 1
78
79 0:
80 # mask = (mask >> 1) | mask
81
82 srw \lower, \mask, \upper
83 or \mask, \mask, \lower
84
85 bdnz 0b
86
87 # mask = mask & 0x07ff
88 # (BAT can map up to 256 MB)
89
90 andi. \mask, \mask, 0x07ff
91
92 # mask = (mask << 2) | 0x0002
93 # (priviledged access only)
94
95 li \upper, 2
96 slw \mask, \mask, \upper
97 ori \mask, \mask, 0x0002
98
99 lis \upper, (0x8000 + \base)
100 or \upper, \upper, \mask
101
102 lis \lower, \base
103 ori \lower, \lower, 0x0002
104.endm
105
106.global start
107.global halt
108.global jump_to_kernel
109.global real_mode
110
111.section BOOTSTRAP, "ax"
112
113start:
114 lis r4, ofw_cif@ha
115 addi r4, r4, ofw_cif@l
116 stw r5, 0(r4)
117
118 bl ofw_init
119 b bootstrap
120
121.text
122
123halt:
124 b halt
125
126jump_to_kernel:
127
128 # arguments:
129 # r3 = bootinfo (physical address)
130 # r4 = translate table (physical address)
131 # r5 = pages to translate
132 # r6 = real mode meeting point (physical address)
133
134 # disable interrupts
135
136 mfmsr r31
137 rlwinm r31, r31, 0, 17, 15
138 mtmsr r31
139
140 # set real mode meeting point physical address
141
142 mtspr srr0, r6
143
144 # jump to real_mode
145
146 mfmsr r31
147 lis r30, ~0@h
148 ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
149 and r31, r31, r30
150 mtspr srr1, r31
151
152 sync
153 isync
154 rfi
155
156.section REALMODE, "ax"
157
158.align PAGE_WIDTH
159real_mode:
160
161 # arguments:
162 # r3 = bootinfo (physical address)
163 # r4 = translate table (physical address)
164 # r5 = pages to translate
165
166 # move the images of components to the proper
167 # location using the translate table
168
169 li r31, PAGE_SIZE >> 2
170 li r30, 0
171
172 page_copy:
173
174 cmpwi r5, 0
175 beq copy_end
176
177 mtctr r31
178 lwz r29, 0(r4)
179
180 copy_loop:
181
182 lwz r28, 0(r29)
183 stw r28, 0(r30)
184
185 SMC_COHERENCY r30
186
187 addi r29, r29, 4
188 addi r30, r30, 4
189
190 bdnz copy_loop
191
192 addi r4, r4, 4
193 subi r5, r5, 1
194 b page_copy
195
196 copy_end:
197
198 # initially fill segment registers
199
200 li r31, 0
201
202 li r29, 8
203 mtctr r29
204 li r30, 0 # ASID 0 (VSIDs 0 .. 7)
205
206 seg_fill_uspace:
207
208 mtsrin r30, r31
209 addi r30, r30, 1
210 addis r31, r31, 0x1000 # move to next SR
211
212 bdnz seg_fill_uspace
213
214 li r29, 8
215 mtctr r29
216 lis r30, 0x4000 # priviledged access only
217 ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
218
219 seg_fill_kernel:
220
221 mtsrin r30, r31
222 addi r30, r30, 1
223 addis r31, r31, 0x1000 # move to next SR
224
225 bdnz seg_fill_kernel
226
227 # invalidate block address translation registers
228
229 li r30, 0
230
231 mtspr ibat0u, r30
232 mtspr ibat0l, r30
233
234 mtspr ibat1u, r30
235 mtspr ibat1l, r30
236
237 mtspr ibat2u, r30
238 mtspr ibat2l, r30
239
240 mtspr ibat3u, r30
241 mtspr ibat3l, r30
242
243 mtspr dbat0u, r30
244 mtspr dbat0l, r30
245
246 mtspr dbat1u, r30
247 mtspr dbat1l, r30
248
249 mtspr dbat2u, r30
250 mtspr dbat2l, r30
251
252 mtspr dbat3u, r30
253 mtspr dbat3l, r30
254
255 # create empty Page Hash Table
256 # on top of memory, size 64 KB
257
258 lwz r31, 4(r3) # r31 = memory size
259
260 lis r30, 65536@h
261 ori r30, r30, 65536@l # r30 = 65536
262
263 subi r29, r30, 1 # r29 = 65535
264
265 sub r31, r31, r30
266 andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
267
268 mtsdr1 r31
269
270 li r29, 2
271 srw r30, r30, r29 # r30 = 16384
272 li r29, 0
273
274 pht_clear:
275
276 # write zeroes
277
278 stw r29, 0(r31)
279 FLUSH_DCACHE r31
280
281 addi r31, r31, 4
282 subi r30, r30, 4
283
284 cmpwi r30, 0
285 beq clear_end
286
287 bdnz pht_clear
288
289 clear_end:
290
291 # create BAT identity mapping
292
293 lwz r31, 4(r3) # r31 = memory size
294
295 lis r30, 268435456@h
296 ori r30, r30, 268435456@l # r30 = 256 MB
297
298 # BAT0
299
300 # r29 = min(r31, r30)
301
302 cmpw r31, r30
303 blt bat0_r31
304
305 mr r29, r30
306 b bat0_r30
307
308 bat0_r31:
309
310 mr r29, r31
311
312 bat0_r30:
313
314 BAT_COMPUTE 0x0000 r29 r28 r27 r26
315 mtspr ibat0u, r26
316 mtspr ibat0l, r27
317
318 mtspr dbat0u, r26
319 mtspr dbat0l, r27
320
321 # BAT1
322
323 sub r31, r31, r29 # r31 = r31 - r29
324
325 # r29 = min(r31, r30)
326
327 cmpw r31, r30
328 blt bat1_r31
329
330 mr r29, r30
331 b bat1_r30
332
333 bat1_r31:
334
335 mr r29, r31
336
337 bat1_r30:
338
339 BAT_COMPUTE 0x1000 r29 r28 r27 r26
340 mtspr ibat1u, r26
341 mtspr ibat1l, r27
342
343 mtspr dbat1u, r26
344 mtspr dbat1l, r27
345
346 # BAT2
347
348 sub r31, r31, r29 # r31 = r31 - r29
349
350 # r29 = min(r31, r30)
351
352 cmpw r31, r30
353 blt bat2_r31
354
355 mr r29, r30
356 b bat2_r30
357
358 bat2_r31:
359
360 mr r29, r31
361
362 bat2_r30:
363
364 BAT_COMPUTE 0x2000 r29 r28 r27 r26
365 mtspr ibat2u, r26
366 mtspr ibat2l, r27
367
368 mtspr dbat2u, r26
369 mtspr dbat2l, r27
370
371 # BAT3
372
373 sub r31, r31, r29 # r31 = r31 - r29
374
375 # r29 = min(r31, r30)
376
377 cmpw r31, r30
378 blt bat3_r31
379
380 mr r29, r30
381 b bat3_r30
382
383 bat3_r31:
384
385 mr r29, r31
386
387 bat3_r30:
388
389 BAT_COMPUTE 0x3000 r29 r28 r27 r26
390 mtspr ibat3u, r26
391 mtspr ibat3l, r27
392
393 mtspr dbat3u, r26
394 mtspr dbat3l, r27
395
396 no_bat:
397
398 # flush TLB
399
400 TLB_FLUSH r31
401
402 # start the kernel
403 #
404 # pc = PA2KA(BOOT_OFFSET)
405 # r3 = bootinfo (physical address)
406 # sprg0 = BOOT_OFFSET
407 # sprg3 = physical memory size
408 # sp = 0 (enforces the usage of sprg0 as exception stack)
409
410 lis r31, PA2KA(BOOT_OFFSET)@ha
411 addi r31, r31, PA2KA(BOOT_OFFSET)@l
412 mtspr srr0, r31
413
414 lis r31, BOOT_OFFSET@ha
415 addi r31, r31, BOOT_OFFSET@l
416 mtsprg0 r31
417
418 # bootinfo starts with a 64 bit integer containing
419 # the physical memory size, get the lower 4 bytes
420
421 lwz r31, 4(r3)
422 mtsprg3 r31
423
424 li sp, 0
425
426 mfmsr r31
427 ori r31, r31, (msr_ir | msr_dr)@l
428 mtspr srr1, r31
429
430 sync
431 isync
432 rfi
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