| 1 | #
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| 2 | # Copyright (c) 2006 Martin Decky
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | #include <abi/asmtool.h>
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| 30 | #include <arch/arch.h>
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| 31 | #include <arch/regname.h>
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| 32 |
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| 33 | .macro SMC_COHERENCY addr
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| 34 | dcbst 0, \addr
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| 35 | sync
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| 36 | icbi 0, \addr
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| 37 | sync
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| 38 | isync
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| 39 | .endm
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| 40 |
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| 41 | .macro FLUSH_DCACHE addr
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| 42 | dcbst 0, \addr
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| 43 | sync
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| 44 | isync
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| 45 | .endm
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| 46 |
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| 47 | .macro TLB_FLUSH reg
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| 48 | li \reg, 0
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| 49 | sync
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| 50 |
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| 51 | .rept 64
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| 52 | tlbie \reg
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| 53 | addi \reg, \reg, 0x1000
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| 54 | .endr
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| 55 |
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| 56 | eieio
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| 57 | tlbsync
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| 58 | sync
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| 59 | .endm
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| 60 |
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| 61 | .macro BAT_COMPUTE base size mask lower upper
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| 62 | # less than 128 KB -> no BAT
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| 63 |
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| 64 | lis \upper, 0x0002
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| 65 | cmpw \size, \upper
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| 66 | blt no_bat
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| 67 |
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| 68 | # mask = total >> 18
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| 69 |
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| 70 | li \upper, 18
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| 71 | srw \mask, \size, \upper
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| 72 |
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| 73 | # create Block Length mask by replicating
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| 74 | # the leading logical one 14 times
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| 75 |
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| 76 | li \upper, 14
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| 77 | mtctr \mask
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| 78 | li \upper, 1
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| 79 |
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| 80 | 0:
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| 81 | # mask = (mask >> 1) | mask
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| 82 |
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| 83 | srw \lower, \mask, \upper
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| 84 | or \mask, \mask, \lower
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| 85 |
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| 86 | bdnz 0b
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| 87 |
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| 88 | # mask = mask & 0x07ff
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| 89 | # (BAT can map up to 256 MB)
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| 90 |
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| 91 | andi. \mask, \mask, 0x07ff
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| 92 |
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| 93 | # mask = (mask << 2) | 0x0002
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| 94 | # (priviledged access only)
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| 95 |
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| 96 | li \upper, 2
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| 97 | slw \mask, \mask, \upper
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| 98 | ori \mask, \mask, 0x0002
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| 99 |
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| 100 | lis \upper, (0x8000 + \base)
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| 101 | or \upper, \upper, \mask
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| 102 |
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| 103 | lis \lower, \base
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| 104 | ori \lower, \lower, 0x0002
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| 105 | .endm
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| 106 |
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| 107 | .section BOOTSTRAP, "ax"
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| 108 |
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| 109 | SYMBOL(start)
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| 110 | lis r4, ofw_cif@ha
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| 111 | addi r4, r4, ofw_cif@l
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| 112 | stw r5, 0(r4)
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| 113 |
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| 114 | bl ofw_init
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| 115 | b bootstrap
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| 116 |
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| 117 | .text
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| 118 |
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| 119 | FUNCTION_BEGIN(halt)
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| 120 | b halt
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| 121 | FUNCTION_END(halt)
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| 122 |
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| 123 | FUNCTION_BEGIN(jump_to_kernel)
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| 124 | # arguments:
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| 125 | # r3 = bootinfo (physical address)
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| 126 | # r4 = translate table (physical address)
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| 127 | # r5 = pages to translate
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| 128 | # r6 = real mode meeting point (physical address)
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| 129 |
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| 130 | # disable interrupts
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| 131 |
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| 132 | mfmsr r31
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| 133 | rlwinm r31, r31, 0, 17, 15
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| 134 | mtmsr r31
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| 135 |
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| 136 | # set real mode meeting point physical address
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| 137 |
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| 138 | mtspr srr0, r6
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| 139 |
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| 140 | # jump to real_mode
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| 141 |
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| 142 | mfmsr r31
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| 143 | lis r30, ~0@h
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| 144 | ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
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| 145 | and r31, r31, r30
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| 146 | mtspr srr1, r31
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| 147 |
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| 148 | sync
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| 149 | isync
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| 150 | rfi
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| 151 | FUNCTION_END(jump_to_kernel)
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| 152 |
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| 153 | .section REALMODE, "ax"
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| 154 |
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| 155 | .align PAGE_WIDTH
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| 156 | SYMBOL(real_mode)
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| 157 |
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| 158 | # arguments:
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| 159 | # r3 = bootinfo (physical address)
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| 160 | # r4 = translate table (physical address)
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| 161 | # r5 = pages to translate
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| 162 |
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| 163 | # move the images of components to the proper
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| 164 | # location using the translate table
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| 165 |
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| 166 | li r31, PAGE_SIZE >> 2
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| 167 | li r30, 0
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| 168 |
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| 169 | page_copy:
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| 170 |
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| 171 | cmpwi r5, 0
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| 172 | beq copy_end
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| 173 |
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| 174 | mtctr r31
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| 175 | lwz r29, 0(r4)
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| 176 |
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| 177 | copy_loop:
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| 178 |
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| 179 | lwz r28, 0(r29)
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| 180 | stw r28, 0(r30)
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| 181 |
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| 182 | SMC_COHERENCY r30
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| 183 |
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| 184 | addi r29, r29, 4
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| 185 | addi r30, r30, 4
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| 186 |
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| 187 | bdnz copy_loop
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| 188 |
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| 189 | addi r4, r4, 4
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| 190 | subi r5, r5, 1
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| 191 | b page_copy
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| 192 |
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| 193 | copy_end:
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| 194 |
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| 195 | # initially fill segment registers
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| 196 |
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| 197 | li r31, 0
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| 198 |
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| 199 | li r29, 8
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| 200 | mtctr r29
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| 201 | li r30, 0 # ASID 0 (VSIDs 0 .. 7)
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| 202 |
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| 203 | seg_fill_uspace:
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| 204 |
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| 205 | mtsrin r30, r31
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| 206 | addi r30, r30, 1
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| 207 | addis r31, r31, 0x1000 # move to next SR
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| 208 |
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| 209 | bdnz seg_fill_uspace
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| 210 |
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| 211 | li r29, 8
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| 212 | mtctr r29
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| 213 | lis r30, 0x4000 # priviledged access only
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| 214 | ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
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| 215 |
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| 216 | seg_fill_kernel:
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| 217 |
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| 218 | mtsrin r30, r31
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| 219 | addi r30, r30, 1
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| 220 | addis r31, r31, 0x1000 # move to next SR
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| 221 |
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| 222 | bdnz seg_fill_kernel
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| 223 |
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| 224 | # invalidate block address translation registers
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| 225 |
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| 226 | li r30, 0
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| 227 |
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| 228 | mtspr ibat0u, r30
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| 229 | mtspr ibat0l, r30
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| 230 |
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| 231 | mtspr ibat1u, r30
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| 232 | mtspr ibat1l, r30
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| 233 |
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| 234 | mtspr ibat2u, r30
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| 235 | mtspr ibat2l, r30
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| 236 |
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| 237 | mtspr ibat3u, r30
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| 238 | mtspr ibat3l, r30
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| 239 |
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| 240 | mtspr dbat0u, r30
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| 241 | mtspr dbat0l, r30
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| 242 |
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| 243 | mtspr dbat1u, r30
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| 244 | mtspr dbat1l, r30
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| 245 |
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| 246 | mtspr dbat2u, r30
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| 247 | mtspr dbat2l, r30
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| 248 |
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| 249 | mtspr dbat3u, r30
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| 250 | mtspr dbat3l, r30
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| 251 |
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| 252 | # create empty Page Hash Table
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| 253 | # on top of memory, size 64 KB
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| 254 |
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| 255 | lwz r31, 4(r3) # r31 = memory size
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| 256 |
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| 257 | lis r30, 65536@h
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| 258 | ori r30, r30, 65536@l # r30 = 65536
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| 259 |
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| 260 | subi r29, r30, 1 # r29 = 65535
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| 261 |
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| 262 | sub r31, r31, r30
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| 263 | andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
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| 264 |
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| 265 | mtsdr1 r31
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| 266 |
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| 267 | li r29, 2
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| 268 | srw r30, r30, r29 # r30 = 16384
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| 269 | li r29, 0
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| 270 |
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| 271 | pht_clear:
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| 272 |
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| 273 | # write zeroes
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| 274 |
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| 275 | stw r29, 0(r31)
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| 276 | FLUSH_DCACHE r31
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| 277 |
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| 278 | addi r31, r31, 4
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| 279 | subi r30, r30, 4
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| 280 |
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| 281 | cmpwi r30, 0
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| 282 | beq clear_end
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| 283 |
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| 284 | bdnz pht_clear
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| 285 |
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| 286 | clear_end:
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| 287 |
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| 288 | # create BAT identity mapping
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| 289 |
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| 290 | lwz r31, 4(r3) # r31 = memory size
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| 291 |
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| 292 | lis r30, 268435456@h
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| 293 | ori r30, r30, 268435456@l # r30 = 256 MB
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| 294 |
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| 295 | # BAT0
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| 296 |
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| 297 | # r29 = min(r31, r30)
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| 298 |
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| 299 | cmpw r31, r30
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| 300 | blt bat0_r31
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| 301 |
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| 302 | mr r29, r30
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| 303 | b bat0_r30
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| 304 |
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| 305 | bat0_r31:
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| 306 |
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| 307 | mr r29, r31
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| 308 |
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| 309 | bat0_r30:
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| 310 |
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| 311 | BAT_COMPUTE 0x0000 r29 r28 r27 r26
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| 312 | mtspr ibat0u, r26
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| 313 | mtspr ibat0l, r27
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| 314 |
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| 315 | mtspr dbat0u, r26
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| 316 | mtspr dbat0l, r27
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| 317 |
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| 318 | # BAT1
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| 319 |
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| 320 | sub r31, r31, r29 # r31 = r31 - r29
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| 321 |
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| 322 | # r29 = min(r31, r30)
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| 323 |
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| 324 | cmpw r31, r30
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| 325 | blt bat1_r31
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| 326 |
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| 327 | mr r29, r30
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| 328 | b bat1_r30
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| 329 |
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| 330 | bat1_r31:
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| 331 |
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| 332 | mr r29, r31
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| 333 |
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| 334 | bat1_r30:
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| 335 |
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| 336 | BAT_COMPUTE 0x1000 r29 r28 r27 r26
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| 337 | mtspr ibat1u, r26
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| 338 | mtspr ibat1l, r27
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| 339 |
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| 340 | mtspr dbat1u, r26
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| 341 | mtspr dbat1l, r27
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| 342 |
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| 343 | # BAT2
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| 344 |
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| 345 | sub r31, r31, r29 # r31 = r31 - r29
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| 346 |
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| 347 | # r29 = min(r31, r30)
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| 348 |
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| 349 | cmpw r31, r30
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| 350 | blt bat2_r31
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| 351 |
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| 352 | mr r29, r30
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| 353 | b bat2_r30
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| 354 |
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| 355 | bat2_r31:
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| 356 |
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| 357 | mr r29, r31
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| 358 |
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| 359 | bat2_r30:
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| 360 |
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| 361 | BAT_COMPUTE 0x2000 r29 r28 r27 r26
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| 362 | mtspr ibat2u, r26
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| 363 | mtspr ibat2l, r27
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| 364 |
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| 365 | mtspr dbat2u, r26
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| 366 | mtspr dbat2l, r27
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| 367 |
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| 368 | # BAT3
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| 369 |
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| 370 | sub r31, r31, r29 # r31 = r31 - r29
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| 371 |
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| 372 | # r29 = min(r31, r30)
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| 373 |
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| 374 | cmpw r31, r30
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| 375 | blt bat3_r31
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| 376 |
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| 377 | mr r29, r30
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| 378 | b bat3_r30
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| 379 |
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| 380 | bat3_r31:
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| 381 |
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| 382 | mr r29, r31
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| 383 |
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| 384 | bat3_r30:
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| 385 |
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| 386 | BAT_COMPUTE 0x3000 r29 r28 r27 r26
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| 387 | mtspr ibat3u, r26
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| 388 | mtspr ibat3l, r27
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| 389 |
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| 390 | mtspr dbat3u, r26
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| 391 | mtspr dbat3l, r27
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| 392 |
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| 393 | no_bat:
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| 394 |
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| 395 | # flush TLB
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| 396 |
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| 397 | TLB_FLUSH r31
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| 398 |
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| 399 | # start the kernel
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| 400 | #
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| 401 | # pc = PA2KA(BOOT_OFFSET)
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| 402 | # r3 = bootinfo (physical address)
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| 403 | # sprg0 = BOOT_OFFSET
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| 404 | # sprg3 = physical memory size
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| 405 | # sp = 0 (enforces the usage of sprg0 as exception stack)
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| 406 |
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| 407 | lis r31, PA2KA(BOOT_OFFSET)@ha
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| 408 | addi r31, r31, PA2KA(BOOT_OFFSET)@l
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| 409 | mtspr srr0, r31
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| 410 |
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| 411 | lis r31, BOOT_OFFSET@ha
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| 412 | addi r31, r31, BOOT_OFFSET@l
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| 413 | mtsprg0 r31
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| 414 |
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| 415 | # bootinfo starts with a 64 bit integer containing
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| 416 | # the physical memory size, get the lower 4 bytes
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| 417 |
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| 418 | lwz r31, 4(r3)
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| 419 | mtsprg3 r31
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| 420 |
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| 421 | li sp, 0
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| 422 |
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| 423 | mfmsr r31
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| 424 | ori r31, r31, (msr_ir | msr_dr)@l
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| 425 | mtspr srr1, r31
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| 426 |
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| 427 | sync
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| 428 | isync
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| 429 | rfi
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