| 1 | #
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| 2 | # Copyright (c) 2006 Martin Decky
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | #include "asm.h"
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| 30 | #include "regname.h"
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| 31 |
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| 32 | .macro SMC_COHERENCY addr
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| 33 | dcbst 0, \addr
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| 34 | sync
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| 35 | icbi 0, \addr
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| 36 | sync
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| 37 | isync
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| 38 | .endm
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| 39 |
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| 40 | .macro FLUSH_DCACHE addr
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| 41 | dcbst 0, \addr
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| 42 | sync
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| 43 | isync
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| 44 | .endm
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| 45 |
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| 46 | .macro TLB_FLUSH reg
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| 47 | tlbie \reg
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| 48 | addi \reg, \reg, 0x1000
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| 49 | .endm
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| 50 |
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| 51 | .text
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| 52 |
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| 53 | .global halt
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| 54 | .global memcpy
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| 55 | .global jump_to_kernel
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| 56 |
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| 57 | halt:
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| 58 | b halt
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| 59 |
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| 60 | memcpy:
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| 61 | srwi. r7, r5, 3
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| 62 | addi r6, r3, -4
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| 63 | addi r4, r4, -4
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| 64 | beq 2f
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| 65 |
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| 66 | andi. r0, r6, 3
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| 67 | mtctr r7
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| 68 | bne 5f
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| 69 |
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| 70 | 1:
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| 71 |
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| 72 | lwz r7, 4(r4)
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| 73 | lwzu r8, 8(r4)
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| 74 | stw r7, 4(r6)
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| 75 | stwu r8, 8(r6)
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| 76 | bdnz 1b
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| 77 |
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| 78 | andi. r5, r5, 7
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| 79 |
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| 80 | 2:
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| 81 |
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| 82 | cmplwi 0, r5, 4
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| 83 | blt 3f
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| 84 |
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| 85 | lwzu r0, 4(r4)
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| 86 | addi r5, r5, -4
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| 87 | stwu r0, 4(r6)
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| 88 |
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| 89 | 3:
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| 90 |
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| 91 | cmpwi 0, r5, 0
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| 92 | beqlr
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| 93 | mtctr r5
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| 94 | addi r4, r4, 3
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| 95 | addi r6, r6, 3
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| 96 |
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| 97 | 4:
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| 98 |
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| 99 | lbzu r0, 1(r4)
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| 100 | stbu r0, 1(r6)
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| 101 | bdnz 4b
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| 102 | blr
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| 103 |
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| 104 | 5:
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| 105 |
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| 106 | subfic r0, r0, 4
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| 107 | mtctr r0
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| 108 |
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| 109 | 6:
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| 110 |
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| 111 | lbz r7, 4(r4)
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| 112 | addi r4, r4, 1
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| 113 | stb r7, 4(r6)
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| 114 | addi r6, r6, 1
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| 115 | bdnz 6b
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| 116 | subf r5, r0, r5
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| 117 | rlwinm. r7, r5, 32-3, 3, 31
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| 118 | beq 2b
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| 119 | mtctr r7
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| 120 | b 1b
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| 121 |
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| 122 |
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| 123 | jump_to_kernel:
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| 124 |
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| 125 | # r3 = bootinfo (pa)
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| 126 | # r4 = bootinfo_size
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| 127 | # r5 = trans (pa)
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| 128 | # r6 = bytes to copy
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| 129 | # r7 = real_mode (pa)
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| 130 | # r8 = framebuffer (pa)
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| 131 | # r9 = scanline
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| 132 |
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| 133 | # disable interrupts
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| 134 |
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| 135 | mfmsr r31
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| 136 | rlwinm r31, r31, 0, 17, 15
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| 137 | mtmsr r31
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| 138 |
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| 139 | # set real_mode meeting point address
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| 140 |
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| 141 | mtspr srr0, r7
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| 142 |
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| 143 | # jumps to real_mode
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| 144 |
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| 145 | mfmsr r31
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| 146 | lis r30, ~0@h
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| 147 | ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
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| 148 | and r31, r31, r30
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| 149 | mtspr srr1, r31
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| 150 |
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| 151 | sync
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| 152 | isync
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| 153 | rfi
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| 154 |
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| 155 | .section REALMODE, "ax"
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| 156 | .align PAGE_WIDTH
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| 157 | .global real_mode
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| 158 |
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| 159 | real_mode:
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| 160 |
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| 161 | # copy kernel to proper location
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| 162 | #
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| 163 | # r5 = trans (pa)
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| 164 | # r6 = bytes to copy
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| 165 | # r8 = framebuffer (pa)
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| 166 | # r9 = scanline
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| 167 |
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| 168 | li r31, PAGE_SIZE >> 2
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| 169 | li r30, 0
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| 170 |
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| 171 | page_copy:
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| 172 |
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| 173 | cmpwi r6, 0
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| 174 | beq copy_end
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| 175 |
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| 176 | # copy page
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| 177 |
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| 178 | mtctr r31
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| 179 | lwz r29, 0(r5)
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| 180 |
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| 181 | copy_loop:
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| 182 |
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| 183 | lwz r28, 0(r29)
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| 184 | stw r28, 0(r30)
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| 185 |
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| 186 | SMC_COHERENCY r30
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| 187 |
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| 188 | addi r29, r29, 4
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| 189 | addi r30, r30, 4
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| 190 | subi r6, r6, 4
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| 191 |
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| 192 | cmpwi r6, 0
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| 193 | beq copy_end
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| 194 |
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| 195 | bdnz copy_loop
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| 196 |
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| 197 | addi r5, r5, 4
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| 198 | b page_copy
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| 199 |
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| 200 | copy_end:
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| 201 |
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| 202 | # initially fill segment registers
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| 203 |
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| 204 | li r31, 0
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| 205 |
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| 206 | li r29, 8
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| 207 | mtctr r29
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| 208 | li r30, 0 # ASID 0 (VSIDs 0 .. 7)
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| 209 |
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| 210 | seg_fill_uspace:
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| 211 |
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| 212 | mtsrin r30, r31
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| 213 | addi r30, r30, 1
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| 214 | addis r31, r31, 0x1000 # move to next SR
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| 215 |
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| 216 | bdnz seg_fill_uspace
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| 217 |
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| 218 | li r29, 8
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| 219 | mtctr r29
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| 220 | lis r30, 0x4000 # priviledged access only
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| 221 | ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
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| 222 |
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| 223 | seg_fill_kernel:
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| 224 |
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| 225 | mtsrin r30, r31
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| 226 | addi r30, r30, 1
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| 227 | addis r31, r31, 0x1000 # move to next SR
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| 228 |
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| 229 | bdnz seg_fill_kernel
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| 230 |
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| 231 | # invalidate block address translation registers
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| 232 |
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| 233 | li r30, 0
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| 234 |
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| 235 | mtspr ibat0u, r30
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| 236 | mtspr ibat0l, r30
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| 237 |
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| 238 | mtspr ibat1u, r30
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| 239 | mtspr ibat1l, r30
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| 240 |
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| 241 | mtspr ibat2u, r30
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| 242 | mtspr ibat2l, r30
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| 243 |
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| 244 | mtspr ibat3u, r30
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| 245 | mtspr ibat3l, r30
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| 246 |
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| 247 | mtspr dbat0u, r30
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| 248 | mtspr dbat0l, r30
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| 249 |
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| 250 | mtspr dbat1u, r30
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| 251 | mtspr dbat1l, r30
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| 252 |
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| 253 | mtspr dbat2u, r30
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| 254 | mtspr dbat2l, r30
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| 255 |
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| 256 | mtspr dbat3u, r30
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| 257 | mtspr dbat3l, r30
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| 258 |
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| 259 | # create empty Page Hash Table
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| 260 | # on top of memory, size 64 KB
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| 261 |
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| 262 | lwz r31, 0(r3) # r31 = memory size
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| 263 |
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| 264 | lis r30, 65536@h
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| 265 | ori r30, r30, 65536@l # r30 = 65536
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| 266 |
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| 267 | subi r29, r30, 1 # r29 = 65535
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| 268 |
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| 269 | sub r31, r31, r30
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| 270 | andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
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| 271 |
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| 272 | mtsdr1 r31
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| 273 |
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| 274 | li r29, 2
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| 275 | srw r30, r30, r29 # r30 = 16384
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| 276 | li r29, 0
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| 277 |
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| 278 | pht_clear:
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| 279 |
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| 280 | # write zeroes
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| 281 |
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| 282 | stw r29, 0(r31)
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| 283 | FLUSH_DCACHE r31
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| 284 |
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| 285 | addi r31, r31, 4
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| 286 | subi r30, r30, 4
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| 287 |
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| 288 | cmpwi r30, 0
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| 289 | beq clear_end
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| 290 |
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| 291 | bdnz pht_clear
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| 292 |
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| 293 | clear_end:
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| 294 |
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| 295 | #ifdef CONFIG_BAT
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| 296 |
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| 297 | # create BAT identity mapping
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| 298 |
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| 299 | lwz r31, 0(r3) # r31 = memory size
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| 300 |
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| 301 | lis r29, 0x0002
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| 302 | cmpw r31, r29
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| 303 | blt no_bat # less than 128 KB -> no BAT
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| 304 |
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| 305 | li r29, 18
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| 306 | srw r31, r31, r29 # r31 = total >> 18
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| 307 |
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| 308 | # create Block Length mask by replicating
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| 309 | # the leading logical one 14 times
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| 310 |
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| 311 | li r29, 14
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| 312 | mtctr r31
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| 313 | li r29, 1
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| 314 |
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| 315 | bat_mask:
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| 316 | srw r30, r31, r29 # r30 = mask >> 1
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| 317 | or r31, r31, r30 # mask = mask | r30
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| 318 |
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| 319 | bdnz bat_mask
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| 320 |
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| 321 | andi. r31, r31, 0x07ff # mask = mask & 0x07ff (BAT can map up to 256 MB)
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| 322 |
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| 323 | li r29, 2
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| 324 | slw r31, r31, r29 # mask = mask << 2
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| 325 | ori r31, r31, 0x0002 # mask = mask | 0x0002 (priviledged access only)
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| 326 |
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| 327 | lis r29, 0x8000
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| 328 | or r29, r29, r31
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| 329 |
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| 330 | lis r30, 0x0000
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| 331 | ori r30, r30, 0x0002
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| 332 |
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| 333 | mtspr ibat0u, r29
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| 334 | mtspr ibat0l, r30
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| 335 |
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| 336 | mtspr dbat0u, r29
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| 337 | mtspr dbat0l, r30
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| 338 |
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| 339 | no_bat:
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| 340 |
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| 341 | #endif
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| 342 |
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| 343 | # flush TLB
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| 344 |
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| 345 | li r31, 0
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| 346 | sync
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| 347 |
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| 348 | TLB_FLUSH r31
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| 349 | TLB_FLUSH r31
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| 350 | TLB_FLUSH r31
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| 351 | TLB_FLUSH r31
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| 352 | TLB_FLUSH r31
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| 353 | TLB_FLUSH r31
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| 354 | TLB_FLUSH r31
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| 355 | TLB_FLUSH r31
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| 356 |
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| 357 | TLB_FLUSH r31
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| 358 | TLB_FLUSH r31
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| 359 | TLB_FLUSH r31
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| 360 | TLB_FLUSH r31
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| 361 | TLB_FLUSH r31
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| 362 | TLB_FLUSH r31
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| 363 | TLB_FLUSH r31
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| 364 | TLB_FLUSH r31
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| 365 |
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| 366 | TLB_FLUSH r31
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| 367 | TLB_FLUSH r31
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| 368 | TLB_FLUSH r31
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| 369 | TLB_FLUSH r31
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| 370 | TLB_FLUSH r31
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| 371 | TLB_FLUSH r31
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| 372 | TLB_FLUSH r31
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| 373 | TLB_FLUSH r31
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| 374 |
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| 375 | TLB_FLUSH r31
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| 376 | TLB_FLUSH r31
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| 377 | TLB_FLUSH r31
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| 378 | TLB_FLUSH r31
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| 379 | TLB_FLUSH r31
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| 380 | TLB_FLUSH r31
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| 381 | TLB_FLUSH r31
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| 382 | TLB_FLUSH r31
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| 383 |
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| 384 | TLB_FLUSH r31
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| 385 | TLB_FLUSH r31
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| 386 | TLB_FLUSH r31
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| 387 | TLB_FLUSH r31
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| 388 | TLB_FLUSH r31
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| 389 | TLB_FLUSH r31
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| 390 | TLB_FLUSH r31
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| 391 | TLB_FLUSH r31
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| 392 |
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| 393 | TLB_FLUSH r31
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| 394 | TLB_FLUSH r31
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| 395 | TLB_FLUSH r31
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| 396 | TLB_FLUSH r31
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| 397 | TLB_FLUSH r31
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| 398 | TLB_FLUSH r31
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| 399 | TLB_FLUSH r31
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| 400 | TLB_FLUSH r31
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| 401 |
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| 402 | TLB_FLUSH r31
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| 403 | TLB_FLUSH r31
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| 404 | TLB_FLUSH r31
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| 405 | TLB_FLUSH r31
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| 406 | TLB_FLUSH r31
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| 407 | TLB_FLUSH r31
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| 408 | TLB_FLUSH r31
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| 409 | TLB_FLUSH r31
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| 410 |
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| 411 | TLB_FLUSH r31
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| 412 | TLB_FLUSH r31
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| 413 | TLB_FLUSH r31
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| 414 | TLB_FLUSH r31
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| 415 | TLB_FLUSH r31
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| 416 | TLB_FLUSH r31
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| 417 | TLB_FLUSH r31
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| 418 | TLB_FLUSH r31
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| 419 |
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| 420 | eieio
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| 421 | tlbsync
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| 422 | sync
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| 423 |
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| 424 | # start the kernel
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| 425 | #
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| 426 | # pc = KERNEL_START_ADDR
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| 427 | # r3 = bootinfo (pa)
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| 428 | # sprg0 = KA2PA(KERNEL_START_ADDR)
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| 429 | # sprg3 = physical memory size
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| 430 | # sp = 0 (pa)
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| 431 |
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| 432 | lis r31, KERNEL_START_ADDR@ha
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| 433 | addi r31, r31, KERNEL_START_ADDR@l
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| 434 |
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| 435 | mtspr srr0, r31
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| 436 |
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| 437 | subis r31, r31, 0x8000
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| 438 | mtsprg0 r31
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| 439 |
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| 440 | lwz r31, 0(r3)
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| 441 | mtsprg3 r31
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| 442 |
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| 443 | li sp, 0
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| 444 |
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| 445 | mfmsr r31
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| 446 | ori r31, r31, (msr_ir | msr_dr)@l
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| 447 | mtspr srr1, r31
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| 448 |
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| 449 | sync
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| 450 | isync
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| 451 | rfi
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| 452 |
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| 453 | .align PAGE_WIDTH
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| 454 | .global trans
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| 455 | trans:
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| 456 | .space (TRANS_SIZE * TRANS_ITEM_SIZE)
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