source: mainline/boot/arch/mips32/loader/asm.S@ d2e9c47

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d2e9c47 was 3527a93, checked in by Jakub Jermar <jakub@…>, 17 years ago

Add TODO comments to arm32 and mips32 loaders saying that caches must be put
into the coherent state before passing control to the kernel.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1#
2# Copyright (c) 2006 Martin Decky
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include "regname.h"
30
31.set noat
32.set noreorder
33.set nomacro
34
35.text
36
37.global halt
38.global memcpy
39.global jump_to_kernel
40
41halt:
42 b halt
43 nop
44
45memcpy:
46 addiu $v0,$a1,3
47 li $v1,-4 # 0xfffffffffffffffc
48 and $v0,$v0,$v1
49 beq $a1,$v0,3f
50 move $t0,$a0
51
520:
53 beq $a2,$zero,2f
54 move $a3,$zero
55
561:
57 addu $v0,$a1,$a3
58 lbu $a0,0($v0)
59 addu $v1,$t0,$a3
60 addiu $a3,$a3,1
61 bne $a3,$a2,1b
62 sb $a0,0($v1)
63
642:
65 jr $ra
66 move $v0,$a1
67
683:
69 addiu $v0,$a0,3
70 and $v0,$v0,$v1
71 bne $a0,$v0,0b
72 srl $t1,$a2,2
73
74 beq $t1,$zero,5f
75 move $a3,$zero
76
77 move $a3,$zero
78 move $a0,$zero
794:
80 addu $v0,$a1,$a0
81 lw $v1,0($v0)
82 addiu $a3,$a3,1
83 addu $v0,$t0,$a0
84 sw $v1,0($v0)
85 bne $a3,$t1,4b
86 addiu $a0,$a0,4
87
885:
89 andi $a2,$a2,0x3
90 beq $a2,$zero,2b
91 nop
92
93 sll $v0,$a3,2
94 addu $t1,$v0,$t0
95 move $a3,$zero
96 addu $t0,$v0,$a1
976:
98 addu $v0,$t0,$a3
99 lbu $a0,0($v0)
100 addu $v1,$t1,$a3
101 addiu $a3,$a3,1
102 bne $a3,$a2,6b
103 sb $a0,0($v1)
104
105 jr $ra
106 move $v0,$a1
107
108jump_to_kernel:
109 #
110 # TODO
111 # Make sure that the I-cache, D-cache and memory are mutually coherent
112 # before passing control to the copied code.
113 #
114 j $a0
115 nop
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